clk_mgr/dcn31/dcn31_smu.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef DAL_DC_31_SMU_H_
0027 #define DAL_DC_31_SMU_H_
0028
0029 #ifndef PMFW_DRIVER_IF_H
0030 #define PMFW_DRIVER_IF_H
0031 #define PMFW_DRIVER_IF_VERSION 4
0032
0033 typedef struct {
0034   int32_t value;
0035   uint32_t numFractionalBits;
0036 } FloatInIntFormat_t;
0037
0038 typedef enum {
0039   DSPCLK_DCFCLK = 0,
0040   DSPCLK_DISPCLK,
0041   DSPCLK_PIXCLK,
0042   DSPCLK_PHYCLK,
0043   DSPCLK_COUNT,
0044 } DSPCLK_e;
0045
0046 typedef struct {
0047   uint16_t Freq; // in MHz
0048   uint16_t Vid;  // min voltage in SVI3 VID
0049 } DisplayClockTable_t;
0050
0051 typedef struct {
0052   uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
0053   uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
0054   uint16_t MinMclk;
0055   uint16_t MaxMclk;
0056
0057   uint8_t  WmSetting;
0058   uint8_t  WmType;  // Used for normal pstate change or memory retraining
0059   uint8_t  Padding[2];
0060 } WatermarkRowGeneric_t;
0061
0062 #define NUM_WM_RANGES 4
0063 #define WM_PSTATE_CHG 0
0064 #define WM_RETRAINING 1
0065
0066 typedef enum {
0067   WM_SOCCLK = 0,
0068   WM_DCFCLK,
0069   WM_COUNT,
0070 } WM_CLOCK_e;
0071
0072 typedef struct {
0073   // Watermarks
0074   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0075
0076   uint32_t MmHubPadding[7]; // SMU internal use
0077 } Watermarks_t;
0078
0079 typedef enum {
0080   CUSTOM_DPM_SETTING_GFXCLK,
0081   CUSTOM_DPM_SETTING_CCLK,
0082   CUSTOM_DPM_SETTING_FCLK_CCX,
0083   CUSTOM_DPM_SETTING_FCLK_GFX,
0084   CUSTOM_DPM_SETTING_FCLK_STALLS,
0085   CUSTOM_DPM_SETTING_LCLK,
0086   CUSTOM_DPM_SETTING_COUNT,
0087 } CUSTOM_DPM_SETTING_e;
0088
0089 typedef struct {
0090   uint8_t             ActiveHystLimit;
0091   uint8_t             IdleHystLimit;
0092   uint8_t             FPS;
0093   uint8_t             MinActiveFreqType;
0094   FloatInIntFormat_t  MinActiveFreq;
0095   FloatInIntFormat_t  PD_Data_limit;
0096   FloatInIntFormat_t  PD_Data_time_constant;
0097   FloatInIntFormat_t  PD_Data_error_coeff;
0098   FloatInIntFormat_t  PD_Data_error_rate_coeff;
0099 } DpmActivityMonitorCoeffExt_t;
0100
0101 typedef struct {
0102   DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
0103 } CustomDpmSettings_t;
0104
0105 #define NUM_DCFCLK_DPM_LEVELS   8
0106 #define NUM_DISPCLK_DPM_LEVELS  8
0107 #define NUM_DPPCLK_DPM_LEVELS   8
0108 #define NUM_SOCCLK_DPM_LEVELS   8
0109 #define NUM_VCN_DPM_LEVELS      8
0110 #define NUM_SOC_VOLTAGE_LEVELS  8
0111 #define NUM_DF_PSTATE_LEVELS    4
0112
0113 typedef enum{
0114   WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
0115   WCK_RATIO_1_2,
0116   WCK_RATIO_1_4,
0117   WCK_RATIO_MAX
0118 } WCK_RATIO_e;
0119
0120 typedef struct {
0121   uint32_t FClk;
0122   uint32_t MemClk;
0123   uint32_t Voltage;
0124   uint8_t  WckRatio;
0125   uint8_t  Spare[3];
0126 } DfPstateTable_t;
0127
0128 //Freq in MHz
0129 //Voltage in milli volts with 2 fractional bits
0130 typedef struct {
0131   uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
0132   uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
0133   uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
0134   uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
0135   uint32_t VClocks[NUM_VCN_DPM_LEVELS];
0136   uint32_t DClocks[NUM_VCN_DPM_LEVELS];
0137   uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
0138   DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
0139
0140   uint8_t  NumDcfClkLevelsEnabled;
0141   uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
0142   uint8_t  NumSocClkLevelsEnabled;
0143   uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
0144   uint8_t  NumDfPstatesEnabled;
0145   uint8_t  spare[3];
0146
0147   uint32_t MinGfxClk;
0148   uint32_t MaxGfxClk;
0149 } DpmClocks_t;
0150
0151
0152 // Throttler Status Bitmask
0153 #define THROTTLER_STATUS_BIT_SPL            0
0154 #define THROTTLER_STATUS_BIT_FPPT           1
0155 #define THROTTLER_STATUS_BIT_SPPT           2
0156 #define THROTTLER_STATUS_BIT_SPPT_APU       3
0157 #define THROTTLER_STATUS_BIT_THM_CORE       4
0158 #define THROTTLER_STATUS_BIT_THM_GFX        5
0159 #define THROTTLER_STATUS_BIT_THM_SOC        6
0160 #define THROTTLER_STATUS_BIT_TDC_VDD        7
0161 #define THROTTLER_STATUS_BIT_TDC_SOC        8
0162 #define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
0163 #define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
0164 #define THROTTLER_STATUS_BIT_EDC_CPU       11
0165 #define THROTTLER_STATUS_BIT_EDC_GFX       12
0166
0167 typedef struct {
0168   uint16_t GfxclkFrequency;             //[MHz]
0169   uint16_t SocclkFrequency;             //[MHz]
0170   uint16_t VclkFrequency;               //[MHz]
0171   uint16_t DclkFrequency;               //[MHz]
0172   uint16_t MemclkFrequency;             //[MHz]
0173   uint16_t spare;
0174
0175   uint16_t GfxActivity;                 //[centi]
0176   uint16_t UvdActivity;                 //[centi]
0177
0178   uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
0179   uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
0180   uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
0181
0182   //3rd party tools in Windows need this info in the case of APUs
0183   uint16_t CoreFrequency[8];            //[MHz]
0184   uint16_t CorePower[8];                //[mW]
0185   uint16_t CoreTemperature[8];          //[centi-Celsius]
0186   uint16_t L3Frequency;                 //[MHz]
0187   uint16_t L3Temperature;               //[centi-Celsius]
0188
0189   uint16_t GfxTemperature;              //[centi-Celsius]
0190   uint16_t SocTemperature;              //[centi-Celsius]
0191   uint16_t ThrottlerStatus;
0192
0193   uint16_t CurrentSocketPower;          //[mW]
0194   uint16_t StapmOriginalLimit;          //[W]
0195   uint16_t StapmCurrentLimit;           //[W]
0196   uint16_t ApuPower;                    //[W]
0197   uint16_t dGpuPower;                   //[W]
0198
0199   uint16_t VddTdcValue;                 //[mA]
0200   uint16_t SocTdcValue;                 //[mA]
0201   uint16_t VddEdcValue;                 //[mA]
0202   uint16_t SocEdcValue;                 //[mA]
0203
0204   uint16_t InfrastructureCpuMaxFreq;    //[MHz]
0205   uint16_t InfrastructureGfxMaxFreq;    //[MHz]
0206 } SmuMetrics_t;
0207
0208
0209 // Workload bits
0210 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
0211 #define WORKLOAD_PPLIB_VIDEO_BIT          2
0212 #define WORKLOAD_PPLIB_VR_BIT             3
0213 #define WORKLOAD_PPLIB_COMPUTE_BIT        4
0214 #define WORKLOAD_PPLIB_CUSTOM_BIT         5
0215 #define WORKLOAD_PPLIB_COUNT              6
0216
0217 #define TABLE_BIOS_IF            0 // Called by BIOS
0218 #define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
0219 #define TABLE_CUSTOM_DPM         2 // Called by Driver
0220 #define TABLE_SPARE1             3
0221 #define TABLE_DPMCLOCKS          4 // Called by Driver
0222 #define TABLE_MOMENTARY_PM       5 // Called by Tools
0223 #define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
0224 #define TABLE_SMU_METRICS        7 // Called by Driver
0225 #define TABLE_COUNT              8
0226
0227 #endif
0228
0229 struct dcn31_watermarks {
0230   // Watermarks
0231   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0232
0233   uint32_t MmHubPadding[7]; // SMU internal use
0234 };
0235
0236 struct dcn31_smu_dpm_clks {
0237     DpmClocks_t *dpm_clks;
0238     union large_integer mc_address;
0239 };
0240
0241 /* TODO: taken from vgh, may not be correct */
0242 struct display_idle_optimization {
0243     unsigned int df_request_disabled : 1;
0244     unsigned int phy_ref_clk_off     : 1;
0245     unsigned int s0i2_rdy            : 1;
0246     unsigned int reserved            : 29;
0247 };
0248
0249 union display_idle_optimization_u {
0250     struct display_idle_optimization idle_info;
0251     uint32_t data;
0252 };
0253
0254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
0255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
0256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
0257 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
0258 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
0259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
0260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
0261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
0262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
0263 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
0264 void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
0265 void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
0266 void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
0267
0268 void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);
0269 void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
0270
0271 #endif /* DAL_DC_31_SMU_H_ */