clk_mgr/dcn301/dcn301_smu.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef DAL_DC_301_SMU_H_
0027 #define DAL_DC_301_SMU_H_
0028
0029 #define SMU13_DRIVER_IF_VERSION 2
0030
0031 typedef struct {
0032     uint32_t fclk;
0033     uint32_t memclk;
0034     uint32_t voltage;
0035 } df_pstate_t;
0036
0037 typedef struct {
0038     uint32_t vclk;
0039     uint32_t dclk;
0040 } vcn_clk_t;
0041
0042 typedef enum {
0043     DSPCLK_DCFCLK = 0,
0044     DSPCLK_DISPCLK,
0045     DSPCLK_PIXCLK,
0046     DSPCLK_PHYCLK,
0047     DSPCLK_COUNT,
0048 } DSPCLK_e;
0049
0050 typedef struct {
0051     uint16_t Freq; // in MHz
0052     uint16_t Vid;  // min voltage in SVI2 VID
0053 } DisplayClockTable_t;
0054
0055 typedef struct {
0056     uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
0057     uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
0058     uint16_t MinMclk;
0059     uint16_t MaxMclk;
0060
0061     uint8_t  WmSetting;
0062     uint8_t  WmType;  // Used for normal pstate change or memory retraining
0063     uint8_t  Padding[2];
0064 } WatermarkRowGeneric_t;
0065
0066
0067 #define NUM_WM_RANGES 4
0068
0069 typedef enum {
0070     WM_SOCCLK = 0,
0071     WM_DCFCLK,
0072     WM_COUNT,
0073 } WM_CLOCK_e;
0074
0075 typedef struct {
0076   // Watermarks
0077     WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0078
0079     uint32_t     MmHubPadding[7]; // SMU internal use
0080 } Watermarks_t;
0081
0082
0083 #define TABLE_WATERMARKS         1
0084 #define TABLE_DPMCLOCKS          4 // Called by Driver
0085
0086
0087 #define VG_NUM_DCFCLK_DPM_LEVELS   7
0088 #define VG_NUM_DISPCLK_DPM_LEVELS  7
0089 #define VG_NUM_DPPCLK_DPM_LEVELS   7
0090 #define VG_NUM_SOCCLK_DPM_LEVELS   7
0091 #define VG_NUM_ISPICLK_DPM_LEVELS  7
0092 #define VG_NUM_ISPXCLK_DPM_LEVELS  7
0093 #define VG_NUM_VCN_DPM_LEVELS      5
0094 #define VG_NUM_FCLK_DPM_LEVELS     4
0095 #define VG_NUM_SOC_VOLTAGE_LEVELS  8
0096
0097 // copy from vgh/vangogh/pmfw_driver_if.h
0098 struct vg_dpm_clocks {
0099     uint32_t DcfClocks[VG_NUM_DCFCLK_DPM_LEVELS];
0100     uint32_t DispClocks[VG_NUM_DISPCLK_DPM_LEVELS];
0101     uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS];
0102     uint32_t SocClocks[VG_NUM_SOCCLK_DPM_LEVELS];
0103     uint32_t IspiClocks[VG_NUM_ISPICLK_DPM_LEVELS];
0104     uint32_t IspxClocks[VG_NUM_ISPXCLK_DPM_LEVELS];
0105     vcn_clk_t VcnClocks[VG_NUM_VCN_DPM_LEVELS];
0106
0107     uint32_t SocVoltage[VG_NUM_SOC_VOLTAGE_LEVELS];
0108
0109     df_pstate_t DfPstateTable[VG_NUM_FCLK_DPM_LEVELS];
0110
0111     uint32_t MinGfxClk;
0112     uint32_t MaxGfxClk;
0113
0114     uint8_t NumDfPstatesEnabled;
0115     uint8_t NumDcfclkLevelsEnabled;
0116     uint8_t NumDispClkLevelsEnabled;  //applies to both dispclk and dppclk
0117     uint8_t NumSocClkLevelsEnabled;
0118
0119     uint8_t IspClkLevelsEnabled;  //applies to both ispiclk and ispxclk
0120     uint8_t VcnClkLevelsEnabled;  //applies to both vclk/dclk
0121     uint8_t spare[2];
0122 };
0123
0124 struct smu_dpm_clks {
0125     struct vg_dpm_clocks *dpm_clks;
0126     union large_integer mc_address;
0127 };
0128
0129 struct watermarks {
0130   // Watermarks
0131     WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0132
0133     uint32_t     MmHubPadding[7]; // SMU internal use
0134 };
0135
0136
0137 struct display_idle_optimization {
0138     unsigned int df_request_disabled : 1;
0139     unsigned int phy_ref_clk_off     : 1;
0140     unsigned int s0i2_rdy            : 1;
0141     unsigned int reserved            : 29;
0142 };
0143
0144 union display_idle_optimization_u {
0145     struct display_idle_optimization idle_info;
0146     uint32_t data;
0147 };
0148
0149
0150 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
0151 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
0152 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
0153 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
0154 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
0155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
0156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
0157 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
0158 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
0159 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
0160 void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
0161 void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
0162 void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
0163
0164 #endif /* DAL_DC_301_SMU_H_ */