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0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #undef TRACE_SYSTEM
0027 #define TRACE_SYSTEM amdgpu_dm
0028 
0029 #if !defined(_AMDGPU_DM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
0030 #define _AMDGPU_DM_TRACE_H_
0031 
0032 #include <linux/tracepoint.h>
0033 #include <drm/drm_connector.h>
0034 #include <drm/drm_crtc.h>
0035 #include <drm/drm_plane.h>
0036 #include <drm/drm_fourcc.h>
0037 #include <drm/drm_framebuffer.h>
0038 #include <drm/drm_encoder.h>
0039 #include <drm/drm_atomic.h>
0040 
0041 #include "dc/inc/core_types.h"
0042 
0043 DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
0044             TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
0045             TP_ARGS(count, reg, value),
0046 
0047             TP_STRUCT__entry(
0048                      __field(uint32_t, reg)
0049                      __field(uint32_t, value)
0050             ),
0051 
0052             TP_fast_assign(
0053                    __entry->reg = reg;
0054                    __entry->value = value;
0055                    *count = *count + 1;
0056             ),
0057 
0058             TP_printk("reg=0x%08lx, value=0x%08lx",
0059                   (unsigned long)__entry->reg,
0060                   (unsigned long)__entry->value)
0061 );
0062 
0063 DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg,
0064          TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
0065          TP_ARGS(count, reg, value));
0066 
0067 DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg,
0068          TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
0069          TP_ARGS(count, reg, value));
0070 
0071 TRACE_EVENT(amdgpu_dc_performance,
0072     TP_PROTO(unsigned long read_count, unsigned long write_count,
0073         unsigned long *last_read, unsigned long *last_write,
0074         const char *func, unsigned int line),
0075     TP_ARGS(read_count, write_count, last_read, last_write, func, line),
0076     TP_STRUCT__entry(
0077             __field(uint32_t, reads)
0078             __field(uint32_t, writes)
0079             __field(uint32_t, read_delta)
0080             __field(uint32_t, write_delta)
0081             __string(func, func)
0082             __field(uint32_t, line)
0083             ),
0084     TP_fast_assign(
0085             __entry->reads = read_count;
0086             __entry->writes = write_count;
0087             __entry->read_delta = read_count - *last_read;
0088             __entry->write_delta = write_count - *last_write;
0089             __assign_str(func, func);
0090             __entry->line = line;
0091             *last_read = read_count;
0092             *last_write = write_count;
0093             ),
0094     TP_printk("%s:%d reads=%08ld (%08ld total), writes=%08ld (%08ld total)",
0095             __get_str(func), __entry->line,
0096             (unsigned long)__entry->read_delta,
0097             (unsigned long)__entry->reads,
0098             (unsigned long)__entry->write_delta,
0099             (unsigned long)__entry->writes)
0100 );
0101 
0102 TRACE_EVENT(amdgpu_dm_connector_atomic_check,
0103         TP_PROTO(const struct drm_connector_state *state),
0104         TP_ARGS(state),
0105 
0106         TP_STRUCT__entry(
0107                  __field(uint32_t, conn_id)
0108                  __field(const struct drm_connector_state *, conn_state)
0109                  __field(const struct drm_atomic_state *, state)
0110                  __field(const struct drm_crtc_commit *, commit)
0111                  __field(uint32_t, crtc_id)
0112                  __field(uint32_t, best_encoder_id)
0113                  __field(enum drm_link_status, link_status)
0114                  __field(bool, self_refresh_aware)
0115                  __field(enum hdmi_picture_aspect, picture_aspect_ratio)
0116                  __field(unsigned int, content_type)
0117                  __field(unsigned int, hdcp_content_type)
0118                  __field(unsigned int, content_protection)
0119                  __field(unsigned int, scaling_mode)
0120                  __field(u32, colorspace)
0121                  __field(u8, max_requested_bpc)
0122                  __field(u8, max_bpc)
0123         ),
0124 
0125         TP_fast_assign(
0126                __entry->conn_id = state->connector->base.id;
0127                __entry->conn_state = state;
0128                __entry->state = state->state;
0129                __entry->commit = state->commit;
0130                __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
0131                __entry->best_encoder_id = state->best_encoder ?
0132                               state->best_encoder->base.id : 0;
0133                __entry->link_status = state->link_status;
0134                __entry->self_refresh_aware = state->self_refresh_aware;
0135                __entry->picture_aspect_ratio = state->picture_aspect_ratio;
0136                __entry->content_type = state->content_type;
0137                __entry->hdcp_content_type = state->hdcp_content_type;
0138                __entry->content_protection = state->content_protection;
0139                __entry->scaling_mode = state->scaling_mode;
0140                __entry->colorspace = state->colorspace;
0141                __entry->max_requested_bpc = state->max_requested_bpc;
0142                __entry->max_bpc = state->max_bpc;
0143         ),
0144 
0145         TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u "
0146               "best_encoder_id=%u link_status=%d self_refresh_aware=%d "
0147               "picture_aspect_ratio=%d content_type=%u "
0148               "hdcp_content_type=%u content_protection=%u scaling_mode=%u "
0149               "colorspace=%u max_requested_bpc=%u max_bpc=%u",
0150               __entry->conn_id, __entry->conn_state, __entry->state,
0151               __entry->commit, __entry->crtc_id, __entry->best_encoder_id,
0152               __entry->link_status, __entry->self_refresh_aware,
0153               __entry->picture_aspect_ratio, __entry->content_type,
0154               __entry->hdcp_content_type, __entry->content_protection,
0155               __entry->scaling_mode, __entry->colorspace,
0156               __entry->max_requested_bpc, __entry->max_bpc)
0157 );
0158 
0159 TRACE_EVENT(amdgpu_dm_crtc_atomic_check,
0160         TP_PROTO(const struct drm_crtc_state *state),
0161         TP_ARGS(state),
0162 
0163         TP_STRUCT__entry(
0164                  __field(const struct drm_atomic_state *, state)
0165                  __field(const struct drm_crtc_state *, crtc_state)
0166                  __field(const struct drm_crtc_commit *, commit)
0167                  __field(uint32_t, crtc_id)
0168                  __field(bool, enable)
0169                  __field(bool, active)
0170                  __field(bool, planes_changed)
0171                  __field(bool, mode_changed)
0172                  __field(bool, active_changed)
0173                  __field(bool, connectors_changed)
0174                  __field(bool, zpos_changed)
0175                  __field(bool, color_mgmt_changed)
0176                  __field(bool, no_vblank)
0177                  __field(bool, async_flip)
0178                  __field(bool, vrr_enabled)
0179                  __field(bool, self_refresh_active)
0180                  __field(u32, plane_mask)
0181                  __field(u32, connector_mask)
0182                  __field(u32, encoder_mask)
0183         ),
0184 
0185         TP_fast_assign(
0186                __entry->state = state->state;
0187                __entry->crtc_state = state;
0188                __entry->crtc_id = state->crtc->base.id;
0189                __entry->commit = state->commit;
0190                __entry->enable = state->enable;
0191                __entry->active = state->active;
0192                __entry->planes_changed = state->planes_changed;
0193                __entry->mode_changed = state->mode_changed;
0194                __entry->active_changed = state->active_changed;
0195                __entry->connectors_changed = state->connectors_changed;
0196                __entry->zpos_changed = state->zpos_changed;
0197                __entry->color_mgmt_changed = state->color_mgmt_changed;
0198                __entry->no_vblank = state->no_vblank;
0199                __entry->async_flip = state->async_flip;
0200                __entry->vrr_enabled = state->vrr_enabled;
0201                __entry->self_refresh_active = state->self_refresh_active;
0202                __entry->plane_mask = state->plane_mask;
0203                __entry->connector_mask = state->connector_mask;
0204                __entry->encoder_mask = state->encoder_mask;
0205         ),
0206 
0207         TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed("
0208               "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) "
0209               "state(enable=%d active=%d async_flip=%d vrr_enabled=%d "
0210               "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x "
0211               "enc=%x)",
0212               __entry->crtc_id, __entry->crtc_state, __entry->state,
0213               __entry->commit, __entry->planes_changed,
0214               __entry->mode_changed, __entry->active_changed,
0215               __entry->connectors_changed, __entry->zpos_changed,
0216               __entry->color_mgmt_changed, __entry->enable, __entry->active,
0217               __entry->async_flip, __entry->vrr_enabled,
0218               __entry->self_refresh_active, __entry->no_vblank,
0219               __entry->plane_mask, __entry->connector_mask,
0220               __entry->encoder_mask)
0221 );
0222 
0223 DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template,
0224         TP_PROTO(const struct drm_plane_state *state),
0225         TP_ARGS(state),
0226         TP_STRUCT__entry(
0227                  __field(uint32_t, plane_id)
0228                  __field(enum drm_plane_type, plane_type)
0229                  __field(const struct drm_plane_state *, plane_state)
0230                  __field(const struct drm_atomic_state *, state)
0231                  __field(uint32_t, crtc_id)
0232                  __field(uint32_t, fb_id)
0233                  __field(uint32_t, fb_format)
0234                  __field(uint8_t, fb_planes)
0235                  __field(uint64_t, fb_modifier)
0236                  __field(const struct dma_fence *, fence)
0237                  __field(int32_t, crtc_x)
0238                  __field(int32_t, crtc_y)
0239                  __field(uint32_t, crtc_w)
0240                  __field(uint32_t, crtc_h)
0241                  __field(uint32_t, src_x)
0242                  __field(uint32_t, src_y)
0243                  __field(uint32_t, src_w)
0244                  __field(uint32_t, src_h)
0245                  __field(u32, alpha)
0246                  __field(uint32_t, pixel_blend_mode)
0247                  __field(unsigned int, rotation)
0248                  __field(unsigned int, zpos)
0249                  __field(unsigned int, normalized_zpos)
0250                  __field(enum drm_color_encoding, color_encoding)
0251                  __field(enum drm_color_range, color_range)
0252                  __field(bool, visible)
0253         ),
0254 
0255         TP_fast_assign(
0256                __entry->plane_id = state->plane->base.id;
0257                __entry->plane_type = state->plane->type;
0258                __entry->plane_state = state;
0259                __entry->state = state->state;
0260                __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
0261                __entry->fb_id = state->fb ? state->fb->base.id : 0;
0262                __entry->fb_format = state->fb ? state->fb->format->format : 0;
0263                __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0;
0264                __entry->fb_modifier = state->fb ? state->fb->modifier : 0;
0265                __entry->fence = state->fence;
0266                __entry->crtc_x = state->crtc_x;
0267                __entry->crtc_y = state->crtc_y;
0268                __entry->crtc_w = state->crtc_w;
0269                __entry->crtc_h = state->crtc_h;
0270                __entry->src_x = state->src_x >> 16;
0271                __entry->src_y = state->src_y >> 16;
0272                __entry->src_w = state->src_w >> 16;
0273                __entry->src_h = state->src_h >> 16;
0274                __entry->alpha = state->alpha;
0275                __entry->pixel_blend_mode = state->pixel_blend_mode;
0276                __entry->rotation = state->rotation;
0277                __entry->zpos = state->zpos;
0278                __entry->normalized_zpos = state->normalized_zpos;
0279                __entry->color_encoding = state->color_encoding;
0280                __entry->color_range = state->color_range;
0281                __entry->visible = state->visible;
0282         ),
0283 
0284         TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p "
0285               "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) "
0286               "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u "
0287               "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u "
0288               "pixel_blend_mode=%u rotation=%u zpos=%u "
0289               "normalized_zpos=%u color_encoding=%d color_range=%d "
0290               "visible=%d",
0291               __entry->plane_id, __entry->plane_type, __entry->plane_state,
0292               __entry->state, __entry->crtc_id, __entry->fb_id,
0293               (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N',
0294               ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O',
0295               ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N',
0296               ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E',
0297               __entry->fb_planes,
0298               __entry->fb_modifier, __entry->fence, __entry->crtc_x,
0299               __entry->crtc_y, __entry->crtc_w, __entry->crtc_h,
0300               __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h,
0301               __entry->alpha, __entry->pixel_blend_mode, __entry->rotation,
0302               __entry->zpos, __entry->normalized_zpos,
0303               __entry->color_encoding, __entry->color_range,
0304               __entry->visible)
0305 );
0306 
0307 DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check,
0308          TP_PROTO(const struct drm_plane_state *state),
0309          TP_ARGS(state));
0310 
0311 DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor,
0312          TP_PROTO(const struct drm_plane_state *state),
0313          TP_ARGS(state));
0314 
0315 TRACE_EVENT(amdgpu_dm_atomic_state_template,
0316         TP_PROTO(const struct drm_atomic_state *state),
0317         TP_ARGS(state),
0318 
0319         TP_STRUCT__entry(
0320                  __field(const struct drm_atomic_state *, state)
0321                  __field(bool, allow_modeset)
0322                  __field(bool, legacy_cursor_update)
0323                  __field(bool, async_update)
0324                  __field(bool, duplicated)
0325                  __field(int, num_connector)
0326                  __field(int, num_private_objs)
0327         ),
0328 
0329         TP_fast_assign(
0330                __entry->state = state;
0331                __entry->allow_modeset = state->allow_modeset;
0332                __entry->legacy_cursor_update = state->legacy_cursor_update;
0333                __entry->async_update = state->async_update;
0334                __entry->duplicated = state->duplicated;
0335                __entry->num_connector = state->num_connector;
0336                __entry->num_private_objs = state->num_private_objs;
0337         ),
0338 
0339         TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d "
0340               "async_update=%d duplicated=%d num_connector=%d "
0341               "num_private_objs=%d",
0342               __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update,
0343               __entry->async_update, __entry->duplicated, __entry->num_connector,
0344               __entry->num_private_objs)
0345 );
0346 
0347 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin,
0348          TP_PROTO(const struct drm_atomic_state *state),
0349          TP_ARGS(state));
0350 
0351 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish,
0352          TP_PROTO(const struct drm_atomic_state *state),
0353          TP_ARGS(state));
0354 
0355 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin,
0356          TP_PROTO(const struct drm_atomic_state *state),
0357          TP_ARGS(state));
0358 
0359 TRACE_EVENT(amdgpu_dm_atomic_check_finish,
0360         TP_PROTO(const struct drm_atomic_state *state, int res),
0361         TP_ARGS(state, res),
0362 
0363         TP_STRUCT__entry(
0364                  __field(const struct drm_atomic_state *, state)
0365                  __field(int, res)
0366                  __field(bool, async_update)
0367                  __field(bool, allow_modeset)
0368         ),
0369 
0370         TP_fast_assign(
0371                __entry->state = state;
0372                __entry->res = res;
0373                __entry->async_update = state->async_update;
0374                __entry->allow_modeset = state->allow_modeset;
0375         ),
0376 
0377         TP_printk("state=%p res=%d async_update=%d allow_modeset=%d",
0378               __entry->state, __entry->res,
0379               __entry->async_update, __entry->allow_modeset)
0380 );
0381 
0382 TRACE_EVENT(amdgpu_dm_dc_pipe_state,
0383         TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,
0384              const struct dc_stream_state *stream,
0385              const struct plane_resource *plane_res,
0386              int update_flags),
0387         TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
0388 
0389         TP_STRUCT__entry(
0390                  __field(int, pipe_idx)
0391                  __field(const void *, stream)
0392                  __field(int, stream_w)
0393                  __field(int, stream_h)
0394                  __field(int, dst_x)
0395                  __field(int, dst_y)
0396                  __field(int, dst_w)
0397                  __field(int, dst_h)
0398                  __field(int, src_x)
0399                  __field(int, src_y)
0400                  __field(int, src_w)
0401                  __field(int, src_h)
0402                  __field(int, clip_x)
0403                  __field(int, clip_y)
0404                  __field(int, clip_w)
0405                  __field(int, clip_h)
0406                  __field(int, recout_x)
0407                  __field(int, recout_y)
0408                  __field(int, recout_w)
0409                  __field(int, recout_h)
0410                  __field(int, viewport_x)
0411                  __field(int, viewport_y)
0412                  __field(int, viewport_w)
0413                  __field(int, viewport_h)
0414                  __field(int, flip_immediate)
0415                  __field(int, surface_pitch)
0416                  __field(int, format)
0417                  __field(int, swizzle)
0418                  __field(unsigned int, update_flags)
0419     ),
0420 
0421     TP_fast_assign(
0422                __entry->pipe_idx = pipe_idx;
0423                __entry->stream = stream;
0424                __entry->stream_w = stream->timing.h_addressable;
0425                __entry->stream_h = stream->timing.v_addressable;
0426                __entry->dst_x = plane_state->dst_rect.x;
0427                __entry->dst_y = plane_state->dst_rect.y;
0428                __entry->dst_w = plane_state->dst_rect.width;
0429                __entry->dst_h = plane_state->dst_rect.height;
0430                __entry->src_x = plane_state->src_rect.x;
0431                __entry->src_y = plane_state->src_rect.y;
0432                __entry->src_w = plane_state->src_rect.width;
0433                __entry->src_h = plane_state->src_rect.height;
0434                __entry->clip_x = plane_state->clip_rect.x;
0435                __entry->clip_y = plane_state->clip_rect.y;
0436                __entry->clip_w = plane_state->clip_rect.width;
0437                __entry->clip_h = plane_state->clip_rect.height;
0438                __entry->recout_x = plane_res->scl_data.recout.x;
0439                __entry->recout_y = plane_res->scl_data.recout.y;
0440                __entry->recout_w = plane_res->scl_data.recout.width;
0441                __entry->recout_h = plane_res->scl_data.recout.height;
0442                __entry->viewport_x = plane_res->scl_data.viewport.x;
0443                __entry->viewport_y = plane_res->scl_data.viewport.y;
0444                __entry->viewport_w = plane_res->scl_data.viewport.width;
0445                __entry->viewport_h = plane_res->scl_data.viewport.height;
0446                __entry->flip_immediate = plane_state->flip_immediate;
0447                __entry->surface_pitch = plane_state->plane_size.surface_pitch;
0448                __entry->format = plane_state->format;
0449                __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
0450                __entry->update_flags = update_flags;
0451     ),
0452     TP_printk("pipe_idx=%d stream=%p rct(%d,%d) dst=(%d,%d,%d,%d) "
0453           "src=(%d,%d,%d,%d) clip=(%d,%d,%d,%d) recout=(%d,%d,%d,%d) "
0454           "viewport=(%d,%d,%d,%d) flip_immediate=%d pitch=%d "
0455           "format=%d swizzle=%d update_flags=%x",
0456           __entry->pipe_idx,
0457           __entry->stream,
0458           __entry->stream_w,
0459           __entry->stream_h,
0460           __entry->dst_x,
0461           __entry->dst_y,
0462           __entry->dst_w,
0463           __entry->dst_h,
0464           __entry->src_x,
0465           __entry->src_y,
0466           __entry->src_w,
0467           __entry->src_h,
0468           __entry->clip_x,
0469           __entry->clip_y,
0470           __entry->clip_w,
0471           __entry->clip_h,
0472           __entry->recout_x,
0473           __entry->recout_y,
0474           __entry->recout_w,
0475           __entry->recout_h,
0476           __entry->viewport_x,
0477           __entry->viewport_y,
0478           __entry->viewport_w,
0479           __entry->viewport_h,
0480           __entry->flip_immediate,
0481           __entry->surface_pitch,
0482           __entry->format,
0483           __entry->swizzle,
0484           __entry->update_flags
0485     )
0486 );
0487 
0488 TRACE_EVENT(amdgpu_dm_dc_clocks_state,
0489         TP_PROTO(const struct dc_clocks *clk),
0490         TP_ARGS(clk),
0491 
0492         TP_STRUCT__entry(
0493                  __field(int, dispclk_khz)
0494                  __field(int, dppclk_khz)
0495                  __field(int, disp_dpp_voltage_level_khz)
0496                  __field(int, dcfclk_khz)
0497                  __field(int, socclk_khz)
0498                  __field(int, dcfclk_deep_sleep_khz)
0499                  __field(int, fclk_khz)
0500                  __field(int, phyclk_khz)
0501                  __field(int, dramclk_khz)
0502                  __field(int, p_state_change_support)
0503                  __field(int, prev_p_state_change_support)
0504                  __field(int, pwr_state)
0505                  __field(int, dtm_level)
0506                  __field(int, max_supported_dppclk_khz)
0507                  __field(int, max_supported_dispclk_khz)
0508                  __field(int, bw_dppclk_khz)
0509                  __field(int, bw_dispclk_khz)
0510         ),
0511         TP_fast_assign(
0512                __entry->dispclk_khz = clk->dispclk_khz;
0513                __entry->dppclk_khz = clk->dppclk_khz;
0514                __entry->dcfclk_khz = clk->dcfclk_khz;
0515                __entry->socclk_khz = clk->socclk_khz;
0516                __entry->dcfclk_deep_sleep_khz = clk->dcfclk_deep_sleep_khz;
0517                __entry->fclk_khz = clk->fclk_khz;
0518                __entry->phyclk_khz = clk->phyclk_khz;
0519                __entry->dramclk_khz = clk->dramclk_khz;
0520                __entry->p_state_change_support = clk->p_state_change_support;
0521                __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
0522                __entry->pwr_state = clk->pwr_state;
0523                __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
0524                __entry->dtm_level = clk->dtm_level;
0525                __entry->max_supported_dppclk_khz = clk->max_supported_dppclk_khz;
0526                __entry->max_supported_dispclk_khz = clk->max_supported_dispclk_khz;
0527                __entry->bw_dppclk_khz = clk->bw_dppclk_khz;
0528                __entry->bw_dispclk_khz = clk->bw_dispclk_khz;
0529         ),
0530         TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d "
0531               "dcfclk_deep_sleep_khz=%d fclk_khz=%d phyclk_khz=%d "
0532               "dramclk_khz=%d p_state_change_support=%d "
0533               "prev_p_state_change_support=%d pwr_state=%d prev_p_state_change_support=%d "
0534               "dtm_level=%d max_supported_dppclk_khz=%d max_supported_dispclk_khz=%d "
0535               "bw_dppclk_khz=%d bw_dispclk_khz=%d ",
0536               __entry->dispclk_khz,
0537               __entry->dppclk_khz,
0538               __entry->disp_dpp_voltage_level_khz,
0539               __entry->dcfclk_khz,
0540               __entry->socclk_khz,
0541               __entry->dcfclk_deep_sleep_khz,
0542               __entry->fclk_khz,
0543               __entry->phyclk_khz,
0544               __entry->dramclk_khz,
0545               __entry->p_state_change_support,
0546               __entry->prev_p_state_change_support,
0547               __entry->pwr_state,
0548               __entry->prev_p_state_change_support,
0549               __entry->dtm_level,
0550               __entry->max_supported_dppclk_khz,
0551               __entry->max_supported_dispclk_khz,
0552               __entry->bw_dppclk_khz,
0553               __entry->bw_dispclk_khz
0554         )
0555 );
0556 
0557 TRACE_EVENT(amdgpu_dm_dce_clocks_state,
0558         TP_PROTO(const struct dce_bw_output *clk),
0559         TP_ARGS(clk),
0560 
0561         TP_STRUCT__entry(
0562                  __field(bool, cpuc_state_change_enable)
0563                  __field(bool, cpup_state_change_enable)
0564                  __field(bool, stutter_mode_enable)
0565                  __field(bool, nbp_state_change_enable)
0566                  __field(bool, all_displays_in_sync)
0567                  __field(int, sclk_khz)
0568                  __field(int, sclk_deep_sleep_khz)
0569                  __field(int, yclk_khz)
0570                  __field(int, dispclk_khz)
0571                  __field(int, blackout_recovery_time_us)
0572         ),
0573         TP_fast_assign(
0574                __entry->cpuc_state_change_enable = clk->cpuc_state_change_enable;
0575                __entry->cpup_state_change_enable = clk->cpup_state_change_enable;
0576                __entry->stutter_mode_enable = clk->stutter_mode_enable;
0577                __entry->nbp_state_change_enable = clk->nbp_state_change_enable;
0578                __entry->all_displays_in_sync = clk->all_displays_in_sync;
0579                __entry->sclk_khz = clk->sclk_khz;
0580                __entry->sclk_deep_sleep_khz = clk->sclk_deep_sleep_khz;
0581                __entry->yclk_khz = clk->yclk_khz;
0582                __entry->dispclk_khz = clk->dispclk_khz;
0583                __entry->blackout_recovery_time_us = clk->blackout_recovery_time_us;
0584         ),
0585         TP_printk("cpuc_state_change_enable=%d cpup_state_change_enable=%d stutter_mode_enable=%d "
0586               "nbp_state_change_enable=%d all_displays_in_sync=%d sclk_khz=%d sclk_deep_sleep_khz=%d "
0587               "yclk_khz=%d dispclk_khz=%d blackout_recovery_time_us=%d",
0588               __entry->cpuc_state_change_enable,
0589               __entry->cpup_state_change_enable,
0590               __entry->stutter_mode_enable,
0591               __entry->nbp_state_change_enable,
0592               __entry->all_displays_in_sync,
0593               __entry->sclk_khz,
0594               __entry->sclk_deep_sleep_khz,
0595               __entry->yclk_khz,
0596               __entry->dispclk_khz,
0597               __entry->blackout_recovery_time_us
0598         )
0599 );
0600 
0601 TRACE_EVENT(amdgpu_dmub_trace_high_irq,
0602     TP_PROTO(uint32_t trace_code, uint32_t tick_count, uint32_t param0,
0603          uint32_t param1),
0604     TP_ARGS(trace_code, tick_count, param0, param1),
0605     TP_STRUCT__entry(
0606         __field(uint32_t, trace_code)
0607         __field(uint32_t, tick_count)
0608         __field(uint32_t, param0)
0609         __field(uint32_t, param1)
0610         ),
0611     TP_fast_assign(
0612         __entry->trace_code = trace_code;
0613         __entry->tick_count = tick_count;
0614         __entry->param0 = param0;
0615         __entry->param1 = param1;
0616     ),
0617     TP_printk("trace_code=%u tick_count=%u param0=%u param1=%u",
0618           __entry->trace_code, __entry->tick_count,
0619           __entry->param0, __entry->param1)
0620 );
0621 
0622 TRACE_EVENT(amdgpu_refresh_rate_track,
0623     TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz),
0624     TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz),
0625     TP_STRUCT__entry(
0626         __field(int, crtc_index)
0627         __field(ktime_t, refresh_rate_ns)
0628         __field(uint32_t, refresh_rate_hz)
0629         ),
0630     TP_fast_assign(
0631         __entry->crtc_index = crtc_index;
0632         __entry->refresh_rate_ns = refresh_rate_ns;
0633         __entry->refresh_rate_hz = refresh_rate_hz;
0634     ),
0635     TP_printk("crtc_index=%d refresh_rate=%dHz (%lld)",
0636           __entry->crtc_index,
0637           __entry->refresh_rate_hz,
0638           __entry->refresh_rate_ns)
0639 );
0640 
0641 TRACE_EVENT(dcn_fpu,
0642         TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth),
0643         TP_ARGS(begin, function, line, recursion_depth),
0644 
0645         TP_STRUCT__entry(
0646                  __field(bool, begin)
0647                  __field(const char *, function)
0648                  __field(int, line)
0649                  __field(int, recursion_depth)
0650         ),
0651         TP_fast_assign(
0652                __entry->begin = begin;
0653                __entry->function = function;
0654                __entry->line = line;
0655                __entry->recursion_depth = recursion_depth;
0656         ),
0657         TP_printk("%s: recursion_depth: %d: %s()+%d:",
0658               __entry->begin ? "begin" : "end",
0659               __entry->recursion_depth,
0660               __entry->function,
0661               __entry->line
0662         )
0663 );
0664 
0665 #endif /* _AMDGPU_DM_TRACE_H_ */
0666 
0667 #undef TRACE_INCLUDE_PATH
0668 #define TRACE_INCLUDE_PATH .
0669 #define TRACE_INCLUDE_FILE amdgpu_dm_trace
0670 #include <trace/define_trace.h>
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