display/amdgpu_dm/amdgpu_dm_psr.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "amdgpu_dm_psr.h"
0027 #include "dc.h"
0028 #include "dm_helpers.h"
0029 #include "amdgpu_dm.h"
0030 #include "modules/power/power_helpers.h"
0031
0032 static bool link_supports_psrsu(struct dc_link *link)
0033 {
0034     struct dc *dc = link->ctx->dc;
0035
0036     if (!dc->caps.dmcub_support)
0037         return false;
0038
0039     if (dc->ctx->dce_version < DCN_VERSION_3_1)
0040         return false;
0041
0042     if (!is_psr_su_specific_panel(link))
0043         return false;
0044
0045     if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
0046         !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
0047         return false;
0048
0049     if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
0050         !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
0051         return false;
0052
0053     return true;
0054 }
0055
0056 /*
0057  * amdgpu_dm_set_psr_caps() - set link psr capabilities
0058  * @link: link
0059  *
0060  */
0061 void amdgpu_dm_set_psr_caps(struct dc_link *link)
0062 {
0063     if (!(link->connector_signal & SIGNAL_TYPE_EDP))
0064         return;
0065
0066     if (link->type == dc_connection_none)
0067         return;
0068
0069     if (link->dpcd_caps.psr_info.psr_version == 0) {
0070         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
0071         link->psr_settings.psr_feature_enabled = false;
0072
0073     } else {
0074         if (link_supports_psrsu(link))
0075             link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
0076         else
0077             link->psr_settings.psr_version = DC_PSR_VERSION_1;
0078
0079         link->psr_settings.psr_feature_enabled = true;
0080     }
0081
0082     DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
0083         link->psr_settings.psr_feature_enabled,
0084         link->psr_settings.psr_version,
0085         link->dpcd_caps.psr_info.psr_version,
0086         link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
0087         link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
0088
0089 }
0090
0091 /*
0092  * amdgpu_dm_link_setup_psr() - configure psr link
0093  * @stream: stream state
0094  *
0095  * Return: true if success
0096  */
0097 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
0098 {
0099     struct dc_link *link = NULL;
0100     struct psr_config psr_config = {0};
0101     struct psr_context psr_context = {0};
0102     struct dc *dc = NULL;
0103     bool ret = false;
0104
0105     if (stream == NULL)
0106         return false;
0107
0108     link = stream->link;
0109     dc = link->ctx->dc;
0110
0111     if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
0112         mod_power_calc_psr_configs(&psr_config, link, stream);
0113
0114         /* linux DM specific updating for psr config fields */
0115         psr_config.allow_smu_optimizations =
0116             (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
0117             mod_power_only_edp(dc->current_state, stream);
0118         psr_config.allow_multi_disp_optimizations =
0119             (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
0120
0121         ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
0122
0123     }
0124     DRM_DEBUG_DRIVER("PSR link: %d\n",  link->psr_settings.psr_feature_enabled);
0125
0126     return ret;
0127 }
0128
0129 /*
0130  * amdgpu_dm_psr_enable() - enable psr f/w
0131  * @stream: stream state
0132  *
0133  * Return: true if success
0134  */
0135 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
0136 {
0137     struct dc_link *link = stream->link;
0138     unsigned int vsync_rate_hz = 0;
0139     struct dc_static_screen_params params = {0};
0140     /* Calculate number of static frames before generating interrupt to
0141      * enter PSR.
0142      */
0143     // Init fail safe of 2 frames static
0144     unsigned int num_frames_static = 2;
0145     unsigned int power_opt = 0;
0146     bool psr_enable = true;
0147
0148     DRM_DEBUG_DRIVER("Enabling psr...\n");
0149
0150     vsync_rate_hz = div64_u64(div64_u64((
0151             stream->timing.pix_clk_100hz * 100),
0152             stream->timing.v_total),
0153             stream->timing.h_total);
0154
0155     /* Round up
0156      * Calculate number of frames such that at least 30 ms of time has
0157      * passed.
0158      */
0159     if (vsync_rate_hz != 0) {
0160         unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
0161         num_frames_static = (30000 / frame_time_microsec) + 1;
0162     }
0163
0164     params.triggers.cursor_update = true;
0165     params.triggers.overlay_update = true;
0166     params.triggers.surface_update = true;
0167     params.num_frames = num_frames_static;
0168
0169     dc_stream_set_static_screen_params(link->ctx->dc,
0170                        &stream, 1,
0171                        &params);
0172
0173     /*
0174      * Only enable static-screen optimizations for PSR1. For PSR SU, this
0175      * causes vstartup interrupt issues, used by amdgpu_dm to send vblank
0176      * events.
0177      */
0178     if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
0179         power_opt |= psr_power_opt_z10_static_screen;
0180
0181     return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
0182 }
0183
0184 /*
0185  * amdgpu_dm_psr_disable() - disable psr f/w
0186  * @stream:  stream state
0187  *
0188  * Return: true if success
0189  */
0190 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
0191 {
0192     unsigned int power_opt = 0;
0193     bool psr_enable = false;
0194
0195     DRM_DEBUG_DRIVER("Disabling psr...\n");
0196
0197     return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
0198 }
0199
0200 /*
0201  * amdgpu_dm_psr_disable() - disable psr f/w
0202  * if psr is enabled on any stream
0203  *
0204  * Return: true if success
0205  */
0206 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
0207 {
0208     DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
0209     return dc_set_psr_allow_active(dm->dc, false);
0210 }
0211