display/amdgpu_dm/amdgpu_dm_plane.h

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright 2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #ifndef __AMDGPU_DM_PLANE_H__
0028 #define __AMDGPU_DM_PLANE_H__
0029
0030 #include "dc.h"
0031
0032 void handle_cursor_update(struct drm_plane *plane,
0033               struct drm_plane_state *old_plane_state);
0034
0035 int fill_dc_scaling_info(struct amdgpu_device *adev,
0036              const struct drm_plane_state *state,
0037              struct dc_scaling_info *scaling_info);
0038
0039 int dm_plane_helper_check_state(struct drm_plane_state *state,
0040                 struct drm_crtc_state *new_crtc_state);
0041
0042 int fill_plane_buffer_attributes(struct amdgpu_device *adev,
0043                  const struct amdgpu_framebuffer *afb,
0044                  const enum surface_pixel_format format,
0045                  const enum dc_rotation_angle rotation,
0046                  const uint64_t tiling_flags,
0047                  union dc_tiling_info *tiling_info,
0048                  struct plane_size *plane_size,
0049                  struct dc_plane_dcc_param *dcc,
0050                  struct dc_plane_address *address,
0051                  bool tmz_surface,
0052                  bool force_disable_dcc);
0053
0054 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
0055              struct drm_plane *plane,
0056              unsigned long possible_crtcs,
0057              const struct dc_plane_cap *plane_cap);
0058
0059 const struct drm_format_info *amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
0060
0061 void fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
0062                     bool *per_pixel_alpha, bool *pre_multiplied_alpha,
0063                     bool *global_alpha, int *global_alpha_value);
0064
0065 #endif