display/amdgpu_dm/amdgpu_dm_irq.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_DM_IRQ_H__
0025 #define __AMDGPU_DM_IRQ_H__
0026
0027 #include "irq_types.h" /* DAL irq definitions */
0028
0029 /*
0030  * Display Manager IRQ-related interfaces (for use by DAL).
0031  */
0032
0033 /**
0034  * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'.
0035  *
0036  * This function should be called exactly once - during DM initialization.
0037  *
0038  * Returns:
0039  *  0 - success
0040  *  non-zero - error
0041  */
0042 int amdgpu_dm_irq_init(struct amdgpu_device *adev);
0043
0044 /**
0045  * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'.
0046  *
0047  * This function should be called exactly once - during DM destruction.
0048  *
0049  */
0050 void amdgpu_dm_irq_fini(struct amdgpu_device *adev);
0051
0052 /**
0053  * amdgpu_dm_irq_register_interrupt - register irq handler for Display block.
0054  *
0055  * @adev: AMD DRM device
0056  * @int_params: parameters for the irq
0057  * @ih: pointer to the irq hander function
0058  * @handler_args: arguments which will be passed to ih
0059  *
0060  * Returns:
0061  *  IRQ Handler Index on success.
0062  *  NULL on failure.
0063  *
0064  * Cannot be called from an interrupt handler.
0065  */
0066 void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
0067                        struct dc_interrupt_params *int_params,
0068                        void (*ih)(void *),
0069                        void *handler_args);
0070
0071 /**
0072  * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered
0073  *  by amdgpu_dm_irq_register_interrupt().
0074  *
0075  * @adev: AMD DRM device.
0076  * @ih_index: irq handler index which was returned by
0077  *  amdgpu_dm_irq_register_interrupt
0078  */
0079 void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
0080                     enum dc_irq_source irq_source,
0081                     void *ih_index);
0082
0083 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
0084
0085 void amdgpu_dm_outbox_init(struct amdgpu_device *adev);
0086 void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
0087 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
0088
0089 /**
0090  * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
0091  *
0092  */
0093 int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
0094
0095 /**
0096  * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.
0097  * amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
0098  *
0099  */
0100 int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
0101 int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);
0102
0103 #endif /* __AMDGPU_DM_IRQ_H__ */