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0026 #include "amdgpu_dm_hdcp.h"
0027 #include "amdgpu.h"
0028 #include "amdgpu_dm.h"
0029 #include "dm_helpers.h"
0030 #include <drm/display/drm_hdcp_helper.h>
0031 #include "hdcp_psp.h"
0032
0033
0034
0035
0036
0037 #define PSP_SRM_VERSION_MAX 0xFFFF
0038
0039 static bool
0040 lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
0041 {
0042
0043 struct dc_link *link = handle;
0044 struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
0045 struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
0046
0047 return dm_helpers_submit_i2c(link->ctx, link, &cmd);
0048 }
0049
0050 static bool
0051 lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)
0052 {
0053 struct dc_link *link = handle;
0054
0055 struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, {false, address, size, data} };
0056 struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
0057
0058 return dm_helpers_submit_i2c(link->ctx, link, &cmd);
0059 }
0060
0061 static bool
0062 lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
0063 {
0064 struct dc_link *link = handle;
0065
0066 return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
0067 }
0068
0069 static bool
0070 lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
0071 {
0072 struct dc_link *link = handle;
0073
0074 return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size);
0075 }
0076
0077 static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size)
0078 {
0079
0080 struct ta_hdcp_shared_memory *hdcp_cmd;
0081
0082 if (!psp->hdcp_context.context.initialized) {
0083 DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized.");
0084 return NULL;
0085 }
0086
0087 hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;
0088 memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
0089
0090 hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_GET_SRM;
0091 psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
0092
0093 if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
0094 return NULL;
0095
0096 *srm_version = hdcp_cmd->out_msg.hdcp_get_srm.srm_version;
0097 *srm_size = hdcp_cmd->out_msg.hdcp_get_srm.srm_buf_size;
0098
0099
0100 return hdcp_cmd->out_msg.hdcp_get_srm.srm_buf;
0101 }
0102
0103 static int psp_set_srm(struct psp_context *psp, uint8_t *srm, uint32_t srm_size, uint32_t *srm_version)
0104 {
0105
0106 struct ta_hdcp_shared_memory *hdcp_cmd;
0107
0108 if (!psp->hdcp_context.context.initialized) {
0109 DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized.");
0110 return -EINVAL;
0111 }
0112
0113 hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;
0114 memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
0115
0116 memcpy(hdcp_cmd->in_msg.hdcp_set_srm.srm_buf, srm, srm_size);
0117 hdcp_cmd->in_msg.hdcp_set_srm.srm_buf_size = srm_size;
0118 hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_SET_SRM;
0119
0120 psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
0121
0122 if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS || hdcp_cmd->out_msg.hdcp_set_srm.valid_signature != 1 ||
0123 hdcp_cmd->out_msg.hdcp_set_srm.srm_version == PSP_SRM_VERSION_MAX)
0124 return -EINVAL;
0125
0126 *srm_version = hdcp_cmd->out_msg.hdcp_set_srm.srm_version;
0127 return 0;
0128 }
0129
0130 static void process_output(struct hdcp_workqueue *hdcp_work)
0131 {
0132 struct mod_hdcp_output output = hdcp_work->output;
0133
0134 if (output.callback_stop)
0135 cancel_delayed_work(&hdcp_work->callback_dwork);
0136
0137 if (output.callback_needed)
0138 schedule_delayed_work(&hdcp_work->callback_dwork,
0139 msecs_to_jiffies(output.callback_delay));
0140
0141 if (output.watchdog_timer_stop)
0142 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
0143
0144 if (output.watchdog_timer_needed)
0145 schedule_delayed_work(&hdcp_work->watchdog_timer_dwork,
0146 msecs_to_jiffies(output.watchdog_timer_delay));
0147
0148 schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0));
0149 }
0150
0151 static void link_lock(struct hdcp_workqueue *work, bool lock)
0152 {
0153
0154 int i = 0;
0155
0156 for (i = 0; i < work->max_link; i++) {
0157 if (lock)
0158 mutex_lock(&work[i].mutex);
0159 else
0160 mutex_unlock(&work[i].mutex);
0161 }
0162 }
0163 void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
0164 unsigned int link_index,
0165 struct amdgpu_dm_connector *aconnector,
0166 uint8_t content_type,
0167 bool enable_encryption)
0168 {
0169 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
0170 struct mod_hdcp_display *display = &hdcp_work[link_index].display;
0171 struct mod_hdcp_link *link = &hdcp_work[link_index].link;
0172 struct mod_hdcp_display_query query;
0173
0174 mutex_lock(&hdcp_w->mutex);
0175 hdcp_w->aconnector = aconnector;
0176
0177 query.display = NULL;
0178 mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &query);
0179
0180 if (query.display != NULL) {
0181 memcpy(display, query.display, sizeof(struct mod_hdcp_display));
0182 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
0183
0184 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
0185
0186 if (enable_encryption) {
0187
0188
0189
0190 if (hdcp_work->srm_size > 0)
0191 psp_set_srm(hdcp_work->hdcp.config.psp.handle, hdcp_work->srm, hdcp_work->srm_size,
0192 &hdcp_work->srm_version);
0193
0194 display->adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE;
0195 if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) {
0196 hdcp_w->link.adjust.hdcp1.disable = 0;
0197 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
0198 } else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1) {
0199 hdcp_w->link.adjust.hdcp1.disable = 1;
0200 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1;
0201 }
0202
0203 schedule_delayed_work(&hdcp_w->property_validate_dwork,
0204 msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
0205 } else {
0206 display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
0207 hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
0208 cancel_delayed_work(&hdcp_w->property_validate_dwork);
0209 }
0210
0211 display->state = MOD_HDCP_DISPLAY_ACTIVE;
0212 }
0213
0214 mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
0215
0216 process_output(hdcp_w);
0217 mutex_unlock(&hdcp_w->mutex);
0218 }
0219
0220 static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,
0221 unsigned int link_index,
0222 struct amdgpu_dm_connector *aconnector)
0223 {
0224 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
0225 struct drm_connector_state *conn_state = aconnector->base.state;
0226
0227 mutex_lock(&hdcp_w->mutex);
0228 hdcp_w->aconnector = aconnector;
0229
0230
0231
0232
0233
0234
0235 if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
0236 conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
0237
0238 DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n",
0239 aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms);
0240 }
0241
0242 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
0243
0244 process_output(hdcp_w);
0245 mutex_unlock(&hdcp_w->mutex);
0246 }
0247 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
0248 {
0249 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
0250
0251 mutex_lock(&hdcp_w->mutex);
0252
0253 mod_hdcp_reset_connection(&hdcp_w->hdcp, &hdcp_w->output);
0254
0255 cancel_delayed_work(&hdcp_w->property_validate_dwork);
0256 hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
0257
0258 process_output(hdcp_w);
0259
0260 mutex_unlock(&hdcp_w->mutex);
0261 }
0262
0263 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
0264 {
0265 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
0266
0267 schedule_work(&hdcp_w->cpirq_work);
0268 }
0269
0270
0271
0272
0273 static void event_callback(struct work_struct *work)
0274 {
0275 struct hdcp_workqueue *hdcp_work;
0276
0277 hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue,
0278 callback_dwork);
0279
0280 mutex_lock(&hdcp_work->mutex);
0281
0282 cancel_delayed_work(&hdcp_work->callback_dwork);
0283
0284 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK,
0285 &hdcp_work->output);
0286
0287 process_output(hdcp_work);
0288
0289 mutex_unlock(&hdcp_work->mutex);
0290
0291
0292 }
0293 static void event_property_update(struct work_struct *work)
0294 {
0295
0296 struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, property_update_work);
0297 struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
0298 struct drm_device *dev = hdcp_work->aconnector->base.dev;
0299 long ret;
0300
0301 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0302 mutex_lock(&hdcp_work->mutex);
0303
0304
0305 if (aconnector->base.state && aconnector->base.state->commit) {
0306 ret = wait_for_completion_interruptible_timeout(&aconnector->base.state->commit->hw_done, 10 * HZ);
0307
0308 if (ret == 0) {
0309 DRM_ERROR("HDCP state unknown! Setting it to DESIRED");
0310 hdcp_work->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
0311 }
0312 }
0313
0314 if (aconnector->base.state) {
0315 if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
0316 if (aconnector->base.state->hdcp_content_type ==
0317 DRM_MODE_HDCP_CONTENT_TYPE0 &&
0318 hdcp_work->encryption_status <=
0319 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON)
0320 drm_hdcp_update_content_protection(&aconnector->base,
0321 DRM_MODE_CONTENT_PROTECTION_ENABLED);
0322 else if (aconnector->base.state->hdcp_content_type ==
0323 DRM_MODE_HDCP_CONTENT_TYPE1 &&
0324 hdcp_work->encryption_status ==
0325 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
0326 drm_hdcp_update_content_protection(&aconnector->base,
0327 DRM_MODE_CONTENT_PROTECTION_ENABLED);
0328 } else {
0329 drm_hdcp_update_content_protection(&aconnector->base,
0330 DRM_MODE_CONTENT_PROTECTION_DESIRED);
0331 }
0332 }
0333
0334 mutex_unlock(&hdcp_work->mutex);
0335 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0336 }
0337
0338 static void event_property_validate(struct work_struct *work)
0339 {
0340 struct hdcp_workqueue *hdcp_work =
0341 container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork);
0342 struct mod_hdcp_display_query query;
0343 struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
0344
0345 if (!aconnector)
0346 return;
0347
0348 mutex_lock(&hdcp_work->mutex);
0349
0350 query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
0351 mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, &query);
0352
0353 if (query.encryption_status != hdcp_work->encryption_status) {
0354 hdcp_work->encryption_status = query.encryption_status;
0355 schedule_work(&hdcp_work->property_update_work);
0356 }
0357
0358 mutex_unlock(&hdcp_work->mutex);
0359 }
0360
0361 static void event_watchdog_timer(struct work_struct *work)
0362 {
0363 struct hdcp_workqueue *hdcp_work;
0364
0365 hdcp_work = container_of(to_delayed_work(work),
0366 struct hdcp_workqueue,
0367 watchdog_timer_dwork);
0368
0369 mutex_lock(&hdcp_work->mutex);
0370
0371 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
0372
0373 mod_hdcp_process_event(&hdcp_work->hdcp,
0374 MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
0375 &hdcp_work->output);
0376
0377 process_output(hdcp_work);
0378
0379 mutex_unlock(&hdcp_work->mutex);
0380
0381 }
0382
0383 static void event_cpirq(struct work_struct *work)
0384 {
0385 struct hdcp_workqueue *hdcp_work;
0386
0387 hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work);
0388
0389 mutex_lock(&hdcp_work->mutex);
0390
0391 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output);
0392
0393 process_output(hdcp_work);
0394
0395 mutex_unlock(&hdcp_work->mutex);
0396
0397 }
0398
0399
0400 void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work)
0401 {
0402 int i = 0;
0403
0404 for (i = 0; i < hdcp_work->max_link; i++) {
0405 cancel_delayed_work_sync(&hdcp_work[i].callback_dwork);
0406 cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork);
0407 }
0408
0409 sysfs_remove_bin_file(kobj, &hdcp_work[0].attr);
0410 kfree(hdcp_work->srm);
0411 kfree(hdcp_work->srm_temp);
0412 kfree(hdcp_work);
0413 }
0414
0415
0416 static bool enable_assr(void *handle, struct dc_link *link)
0417 {
0418
0419 struct hdcp_workqueue *hdcp_work = handle;
0420 struct mod_hdcp hdcp = hdcp_work->hdcp;
0421 struct psp_context *psp = hdcp.config.psp.handle;
0422 struct ta_dtm_shared_memory *dtm_cmd;
0423 bool res = true;
0424
0425 if (!psp->dtm_context.context.initialized) {
0426 DRM_INFO("Failed to enable ASSR, DTM TA is not initialized.");
0427 return false;
0428 }
0429
0430 dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf;
0431
0432 mutex_lock(&psp->dtm_context.mutex);
0433 memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
0434
0435 dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE;
0436 dtm_cmd->dtm_in_message.topology_assr_enable.display_topology_dig_be_index = link->link_enc_hw_inst;
0437 dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
0438
0439 psp_dtm_invoke(psp, dtm_cmd->cmd_id);
0440
0441 if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) {
0442 DRM_INFO("Failed to enable ASSR");
0443 res = false;
0444 }
0445
0446 mutex_unlock(&psp->dtm_context.mutex);
0447
0448 return res;
0449 }
0450
0451 static void update_config(void *handle, struct cp_psp_stream_config *config)
0452 {
0453 struct hdcp_workqueue *hdcp_work = handle;
0454 struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx;
0455 int link_index = aconnector->dc_link->link_index;
0456 struct mod_hdcp_display *display = &hdcp_work[link_index].display;
0457 struct mod_hdcp_link *link = &hdcp_work[link_index].link;
0458 struct drm_connector_state *conn_state;
0459 struct dc_sink *sink = NULL;
0460 bool link_is_hdcp14 = false;
0461
0462 if (config->dpms_off) {
0463 hdcp_remove_display(hdcp_work, link_index, aconnector);
0464 return;
0465 }
0466
0467 memset(display, 0, sizeof(*display));
0468 memset(link, 0, sizeof(*link));
0469
0470 display->index = aconnector->base.index;
0471 display->state = MOD_HDCP_DISPLAY_ACTIVE;
0472
0473 if (aconnector->dc_sink)
0474 sink = aconnector->dc_sink;
0475 else if (aconnector->dc_em_sink)
0476 sink = aconnector->dc_em_sink;
0477
0478 if (sink != NULL)
0479 link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal);
0480
0481 display->controller = CONTROLLER_ID_D0 + config->otg_inst;
0482 display->dig_fe = config->dig_fe;
0483 link->dig_be = config->dig_be;
0484 link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
0485 display->stream_enc_idx = config->stream_enc_idx;
0486 link->link_enc_idx = config->link_enc_idx;
0487 link->dio_output_id = config->dio_output_idx;
0488 link->phy_idx = config->phy_idx;
0489
0490 if (sink)
0491 link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal);
0492 link->hdcp_supported_informational = link_is_hdcp14;
0493 link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
0494 link->dp.assr_enabled = config->assr_enabled;
0495 link->dp.mst_enabled = config->mst_enabled;
0496 link->dp.usb4_enabled = config->usb4_enabled;
0497 display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
0498 link->adjust.auth_delay = 3;
0499 link->adjust.hdcp1.disable = 0;
0500 conn_state = aconnector->base.state;
0501
0502 DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
0503 (!!aconnector->base.state) ? aconnector->base.state->content_protection : -1,
0504 (!!aconnector->base.state) ? aconnector->base.state->hdcp_content_type : -1);
0505
0506 if (conn_state)
0507 hdcp_update_display(hdcp_work, link_index, aconnector,
0508 conn_state->hdcp_content_type, false);
0509 }
0510
0511
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0545
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0552
0553
0554
0555
0556
0557 static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buffer,
0558 loff_t pos, size_t count)
0559 {
0560 struct hdcp_workqueue *work;
0561 uint32_t srm_version = 0;
0562
0563 work = container_of(bin_attr, struct hdcp_workqueue, attr);
0564 link_lock(work, true);
0565
0566 memcpy(work->srm_temp + pos, buffer, count);
0567
0568 if (!psp_set_srm(work->hdcp.config.psp.handle, work->srm_temp, pos + count, &srm_version)) {
0569 DRM_DEBUG_DRIVER("HDCP SRM SET version 0x%X", srm_version);
0570 memcpy(work->srm, work->srm_temp, pos + count);
0571 work->srm_size = pos + count;
0572 work->srm_version = srm_version;
0573 }
0574
0575
0576 link_lock(work, false);
0577
0578 return count;
0579 }
0580
0581 static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buffer,
0582 loff_t pos, size_t count)
0583 {
0584 struct hdcp_workqueue *work;
0585 uint8_t *srm = NULL;
0586 uint32_t srm_version;
0587 uint32_t srm_size;
0588 size_t ret = count;
0589
0590 work = container_of(bin_attr, struct hdcp_workqueue, attr);
0591
0592 link_lock(work, true);
0593
0594 srm = psp_get_srm(work->hdcp.config.psp.handle, &srm_version, &srm_size);
0595
0596 if (!srm) {
0597 ret = -EINVAL;
0598 goto ret;
0599 }
0600
0601 if (pos >= srm_size)
0602 ret = 0;
0603
0604 if (srm_size - pos < count) {
0605 memcpy(buffer, srm + pos, srm_size - pos);
0606 ret = srm_size - pos;
0607 goto ret;
0608 }
0609
0610 memcpy(buffer, srm + pos, count);
0611
0612 ret:
0613 link_lock(work, false);
0614 return ret;
0615 }
0616
0617
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0637
0638 static const struct bin_attribute data_attr = {
0639 .attr = {.name = "hdcp_srm", .mode = 0664},
0640 .size = PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE,
0641 .write = srm_data_write,
0642 .read = srm_data_read,
0643 };
0644
0645
0646 struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc)
0647 {
0648
0649 int max_caps = dc->caps.max_links;
0650 struct hdcp_workqueue *hdcp_work;
0651 int i = 0;
0652
0653 hdcp_work = kcalloc(max_caps, sizeof(*hdcp_work), GFP_KERNEL);
0654 if (ZERO_OR_NULL_PTR(hdcp_work))
0655 return NULL;
0656
0657 hdcp_work->srm = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, sizeof(*hdcp_work->srm), GFP_KERNEL);
0658
0659 if (hdcp_work->srm == NULL)
0660 goto fail_alloc_context;
0661
0662 hdcp_work->srm_temp = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, sizeof(*hdcp_work->srm_temp), GFP_KERNEL);
0663
0664 if (hdcp_work->srm_temp == NULL)
0665 goto fail_alloc_context;
0666
0667 hdcp_work->max_link = max_caps;
0668
0669 for (i = 0; i < max_caps; i++) {
0670 mutex_init(&hdcp_work[i].mutex);
0671
0672 INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq);
0673 INIT_WORK(&hdcp_work[i].property_update_work, event_property_update);
0674 INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback);
0675 INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer);
0676 INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
0677
0678 hdcp_work[i].hdcp.config.psp.handle = &adev->psp;
0679 if (dc->ctx->dce_version == DCN_VERSION_3_1 ||
0680 dc->ctx->dce_version == DCN_VERSION_3_14 ||
0681 dc->ctx->dce_version == DCN_VERSION_3_15 ||
0682 dc->ctx->dce_version == DCN_VERSION_3_16)
0683 hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
0684 hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
0685 hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
0686 hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
0687 hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd;
0688 hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd;
0689 }
0690
0691 cp_psp->funcs.update_stream_config = update_config;
0692 cp_psp->funcs.enable_assr = enable_assr;
0693 cp_psp->handle = hdcp_work;
0694
0695
0696 hdcp_work[0].attr = data_attr;
0697 sysfs_bin_attr_init(&hdcp_work[0].attr);
0698
0699 if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr))
0700 DRM_WARN("Failed to create device file hdcp_srm");
0701
0702 return hdcp_work;
0703
0704 fail_alloc_context:
0705 kfree(hdcp_work->srm);
0706 kfree(hdcp_work->srm_temp);
0707 kfree(hdcp_work);
0708
0709 return NULL;
0710
0711
0712
0713 }
0714
0715
0716