display/amdgpu_dm/amdgpu_dm_crc.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
0027 #define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
0028
0029 struct drm_crtc;
0030 struct dm_crtc_state;
0031
0032 enum amdgpu_dm_pipe_crc_source {
0033     AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
0034     AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
0035     AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
0036     AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
0037     AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
0038     AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
0039     AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
0040 };
0041
0042 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
0043 struct crc_window_parm {
0044     uint16_t x_start;
0045     uint16_t y_start;
0046     uint16_t x_end;
0047     uint16_t y_end;
0048     /* CRC windwo is activated or not*/
0049     bool activated;
0050     /* Update crc window during vertical blank or not */
0051     bool update_win;
0052     /* skip reading/writing for few frames */
0053     int skip_frame_cnt;
0054 };
0055
0056 struct crc_rd_work {
0057     struct work_struct notify_ta_work;
0058     /* To protect crc_rd_work carried fields*/
0059     spinlock_t crc_rd_work_lock;
0060     struct drm_crtc *crtc;
0061     uint8_t phy_inst;
0062 };
0063 #endif
0064
0065 static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
0066 {
0067     return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
0068            (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
0069 }
0070
0071 /* amdgpu_dm_crc.c */
0072 #ifdef CONFIG_DEBUG_FS
0073 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
0074                     struct dm_crtc_state *dm_crtc_state,
0075                     enum amdgpu_dm_pipe_crc_source source);
0076 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
0077 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
0078                      const char *src_name,
0079                      size_t *values_cnt);
0080 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
0081                           size_t *count);
0082 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
0083 #else
0084 #define amdgpu_dm_crtc_set_crc_source NULL
0085 #define amdgpu_dm_crtc_verify_crc_source NULL
0086 #define amdgpu_dm_crtc_get_crc_sources NULL
0087 #define amdgpu_dm_crtc_handle_crc_irq(x)
0088 #endif
0089
0090 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
0091 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
0092 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
0093 struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void);
0094 #else
0095 #define amdgpu_dm_crc_window_is_activated(x)
0096 #define amdgpu_dm_crtc_handle_crc_window_irq(x)
0097 #define amdgpu_dm_crtc_secure_display_create_work()
0098 #endif
0099
0100 #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */