amd/amdkfd/kfd_pm4_headers_vi.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
0002 /*
0003  * Copyright 2014-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #ifndef F32_MES_PM4_PACKETS_H
0026 #define F32_MES_PM4_PACKETS_H
0027
0028 #ifndef PM4_MES_HEADER_DEFINED
0029 #define PM4_MES_HEADER_DEFINED
0030 union PM4_MES_TYPE_3_HEADER {
0031     struct {
0032         uint32_t reserved1 : 8; /* < reserved */
0033         uint32_t opcode    : 8; /* < IT opcode */
0034         uint32_t count     : 14;/* < Number of DWORDS - 1 in the
0035                      *   information body
0036                      */
0037         uint32_t type      : 2; /* < packet identifier
0038                      *   It should be 3 for type 3 packets
0039                      */
0040     };
0041     uint32_t u32All;
0042 };
0043 #endif /* PM4_MES_HEADER_DEFINED */
0044
0045 /*--------------------MES_SET_RESOURCES--------------------*/
0046
0047 #ifndef PM4_MES_SET_RESOURCES_DEFINED
0048 #define PM4_MES_SET_RESOURCES_DEFINED
0049 enum mes_set_resources_queue_type_enum {
0050     queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
0051     queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
0052     queue_type__mes_set_resources__hsa_debug_interface_queue = 4
0053 };
0054
0055
0056 struct pm4_mes_set_resources {
0057     union {
0058         union PM4_MES_TYPE_3_HEADER header;     /* header */
0059         uint32_t            ordinal1;
0060     };
0061
0062     union {
0063         struct {
0064             uint32_t vmid_mask:16;
0065             uint32_t unmap_latency:8;
0066             uint32_t reserved1:5;
0067             enum mes_set_resources_queue_type_enum queue_type:3;
0068         } bitfields2;
0069         uint32_t ordinal2;
0070     };
0071
0072     uint32_t queue_mask_lo;
0073     uint32_t queue_mask_hi;
0074     uint32_t gws_mask_lo;
0075     uint32_t gws_mask_hi;
0076
0077     union {
0078         struct {
0079             uint32_t oac_mask:16;
0080             uint32_t reserved2:16;
0081         } bitfields7;
0082         uint32_t ordinal7;
0083     };
0084
0085     union {
0086         struct {
0087         uint32_t gds_heap_base:6;
0088         uint32_t reserved3:5;
0089         uint32_t gds_heap_size:6;
0090         uint32_t reserved4:15;
0091         } bitfields8;
0092         uint32_t ordinal8;
0093     };
0094
0095 };
0096 #endif
0097
0098 /*--------------------MES_RUN_LIST--------------------*/
0099
0100 #ifndef PM4_MES_RUN_LIST_DEFINED
0101 #define PM4_MES_RUN_LIST_DEFINED
0102
0103 struct pm4_mes_runlist {
0104     union {
0105         union PM4_MES_TYPE_3_HEADER   header;            /* header */
0106         uint32_t            ordinal1;
0107     };
0108
0109     union {
0110         struct {
0111             uint32_t reserved1:2;
0112             uint32_t ib_base_lo:30;
0113         } bitfields2;
0114         uint32_t ordinal2;
0115     };
0116
0117     union {
0118         struct {
0119             uint32_t ib_base_hi:16;
0120             uint32_t reserved2:16;
0121         } bitfields3;
0122         uint32_t ordinal3;
0123     };
0124
0125     union {
0126         struct {
0127             uint32_t ib_size:20;
0128             uint32_t chain:1;
0129             uint32_t offload_polling:1;
0130             uint32_t reserved2:1;
0131             uint32_t valid:1;
0132             uint32_t process_cnt:4;
0133             uint32_t reserved3:4;
0134         } bitfields4;
0135         uint32_t ordinal4;
0136     };
0137
0138 };
0139 #endif
0140
0141 /*--------------------MES_MAP_PROCESS--------------------*/
0142
0143 #ifndef PM4_MES_MAP_PROCESS_DEFINED
0144 #define PM4_MES_MAP_PROCESS_DEFINED
0145
0146 struct pm4_mes_map_process {
0147     union {
0148         union PM4_MES_TYPE_3_HEADER header; /* header */
0149         uint32_t ordinal1;
0150     };
0151
0152     union {
0153         struct {
0154             uint32_t pasid:16;
0155             uint32_t reserved1:8;
0156             uint32_t diq_enable:1;
0157             uint32_t process_quantum:7;
0158         } bitfields2;
0159         uint32_t ordinal2;
0160     };
0161
0162     union {
0163         struct {
0164             uint32_t page_table_base:28;
0165             uint32_t reserved3:4;
0166         } bitfields3;
0167         uint32_t ordinal3;
0168     };
0169
0170     uint32_t reserved;
0171
0172     uint32_t sh_mem_bases;
0173     uint32_t sh_mem_config;
0174     uint32_t sh_mem_ape1_base;
0175     uint32_t sh_mem_ape1_limit;
0176
0177     uint32_t sh_hidden_private_base_vmid;
0178
0179     uint32_t reserved2;
0180     uint32_t reserved3;
0181
0182     uint32_t gds_addr_lo;
0183     uint32_t gds_addr_hi;
0184
0185     union {
0186         struct {
0187             uint32_t num_gws:6;
0188             uint32_t reserved4:2;
0189             uint32_t num_oac:4;
0190             uint32_t reserved5:4;
0191             uint32_t gds_size:6;
0192             uint32_t num_queues:10;
0193         } bitfields10;
0194         uint32_t ordinal10;
0195     };
0196
0197     uint32_t completion_signal_lo;
0198     uint32_t completion_signal_hi;
0199
0200 };
0201
0202 #endif
0203
0204 /*--------------------MES_MAP_QUEUES--------------------*/
0205
0206 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
0207 #define PM4_MES_MAP_QUEUES_VI_DEFINED
0208 enum mes_map_queues_queue_sel_vi_enum {
0209     queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
0210 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
0211 };
0212
0213 enum mes_map_queues_queue_type_vi_enum {
0214     queue_type__mes_map_queues__normal_compute_vi = 0,
0215     queue_type__mes_map_queues__debug_interface_queue_vi = 1,
0216     queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
0217 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
0218 };
0219
0220 enum mes_map_queues_engine_sel_vi_enum {
0221     engine_sel__mes_map_queues__compute_vi = 0,
0222     engine_sel__mes_map_queues__sdma0_vi = 2,
0223     engine_sel__mes_map_queues__sdma1_vi = 3
0224 };
0225
0226
0227 struct pm4_mes_map_queues {
0228     union {
0229         union PM4_MES_TYPE_3_HEADER   header;            /* header */
0230         uint32_t            ordinal1;
0231     };
0232
0233     union {
0234         struct {
0235             uint32_t reserved1:4;
0236             enum mes_map_queues_queue_sel_vi_enum queue_sel:2;
0237             uint32_t reserved2:15;
0238             enum mes_map_queues_queue_type_vi_enum queue_type:3;
0239             uint32_t reserved3:2;
0240             enum mes_map_queues_engine_sel_vi_enum engine_sel:3;
0241             uint32_t num_queues:3;
0242         } bitfields2;
0243         uint32_t ordinal2;
0244     };
0245
0246     union {
0247         struct {
0248             uint32_t reserved3:1;
0249             uint32_t check_disable:1;
0250             uint32_t doorbell_offset:21;
0251             uint32_t reserved4:3;
0252             uint32_t queue:6;
0253         } bitfields3;
0254         uint32_t ordinal3;
0255     };
0256
0257     uint32_t mqd_addr_lo;
0258     uint32_t mqd_addr_hi;
0259     uint32_t wptr_addr_lo;
0260     uint32_t wptr_addr_hi;
0261 };
0262 #endif
0263
0264 /*--------------------MES_QUERY_STATUS--------------------*/
0265
0266 #ifndef PM4_MES_QUERY_STATUS_DEFINED
0267 #define PM4_MES_QUERY_STATUS_DEFINED
0268 enum mes_query_status_interrupt_sel_enum {
0269     interrupt_sel__mes_query_status__completion_status = 0,
0270     interrupt_sel__mes_query_status__process_status = 1,
0271     interrupt_sel__mes_query_status__queue_status = 2
0272 };
0273
0274 enum mes_query_status_command_enum {
0275     command__mes_query_status__interrupt_only = 0,
0276     command__mes_query_status__fence_only_immediate = 1,
0277     command__mes_query_status__fence_only_after_write_ack = 2,
0278     command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
0279 };
0280
0281 enum mes_query_status_engine_sel_enum {
0282     engine_sel__mes_query_status__compute = 0,
0283     engine_sel__mes_query_status__sdma0_queue = 2,
0284     engine_sel__mes_query_status__sdma1_queue = 3
0285 };
0286
0287 struct pm4_mes_query_status {
0288     union {
0289         union PM4_MES_TYPE_3_HEADER   header;            /* header */
0290         uint32_t            ordinal1;
0291     };
0292
0293     union {
0294         struct {
0295             uint32_t context_id:28;
0296             enum mes_query_status_interrupt_sel_enum
0297                 interrupt_sel:2;
0298             enum mes_query_status_command_enum command:2;
0299         } bitfields2;
0300         uint32_t ordinal2;
0301     };
0302
0303     union {
0304         struct {
0305             uint32_t pasid:16;
0306             uint32_t reserved1:16;
0307         } bitfields3a;
0308         struct {
0309             uint32_t reserved2:2;
0310             uint32_t doorbell_offset:21;
0311             uint32_t reserved3:2;
0312             enum mes_query_status_engine_sel_enum engine_sel:3;
0313             uint32_t reserved4:4;
0314         } bitfields3b;
0315         uint32_t ordinal3;
0316     };
0317
0318     uint32_t addr_lo;
0319     uint32_t addr_hi;
0320     uint32_t data_lo;
0321     uint32_t data_hi;
0322 };
0323 #endif
0324
0325 /*--------------------MES_UNMAP_QUEUES--------------------*/
0326
0327 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED
0328 #define PM4_MES_UNMAP_QUEUES_DEFINED
0329 enum mes_unmap_queues_action_enum {
0330     action__mes_unmap_queues__preempt_queues = 0,
0331     action__mes_unmap_queues__reset_queues = 1,
0332     action__mes_unmap_queues__disable_process_queues = 2,
0333     action__mes_unmap_queues__reserved = 3
0334 };
0335
0336 enum mes_unmap_queues_queue_sel_enum {
0337     queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
0338     queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
0339     queue_sel__mes_unmap_queues__unmap_all_queues = 2,
0340     queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
0341 };
0342
0343 enum mes_unmap_queues_engine_sel_enum {
0344     engine_sel__mes_unmap_queues__compute = 0,
0345     engine_sel__mes_unmap_queues__sdma0 = 2,
0346     engine_sel__mes_unmap_queues__sdmal = 3
0347 };
0348
0349 struct pm4_mes_unmap_queues {
0350     union {
0351         union PM4_MES_TYPE_3_HEADER   header;            /* header */
0352         uint32_t            ordinal1;
0353     };
0354
0355     union {
0356         struct {
0357             enum mes_unmap_queues_action_enum action:2;
0358             uint32_t reserved1:2;
0359             enum mes_unmap_queues_queue_sel_enum queue_sel:2;
0360             uint32_t reserved2:20;
0361             enum mes_unmap_queues_engine_sel_enum engine_sel:3;
0362             uint32_t num_queues:3;
0363         } bitfields2;
0364         uint32_t ordinal2;
0365     };
0366
0367     union {
0368         struct {
0369             uint32_t pasid:16;
0370             uint32_t reserved3:16;
0371         } bitfields3a;
0372         struct {
0373             uint32_t reserved4:2;
0374             uint32_t doorbell_offset0:21;
0375             uint32_t reserved5:9;
0376         } bitfields3b;
0377         uint32_t ordinal3;
0378     };
0379
0380     union {
0381     struct {
0382             uint32_t reserved6:2;
0383             uint32_t doorbell_offset1:21;
0384             uint32_t reserved7:9;
0385         } bitfields4;
0386         uint32_t ordinal4;
0387     };
0388
0389     union {
0390         struct {
0391             uint32_t reserved8:2;
0392             uint32_t doorbell_offset2:21;
0393             uint32_t reserved9:9;
0394         } bitfields5;
0395         uint32_t ordinal5;
0396     };
0397
0398     union {
0399         struct {
0400             uint32_t reserved10:2;
0401             uint32_t doorbell_offset3:21;
0402             uint32_t reserved11:9;
0403         } bitfields6;
0404         uint32_t ordinal6;
0405     };
0406 };
0407 #endif
0408
0409 #ifndef PM4_MEC_RELEASE_MEM_DEFINED
0410 #define PM4_MEC_RELEASE_MEM_DEFINED
0411 enum RELEASE_MEM_event_index_enum {
0412     event_index___release_mem__end_of_pipe = 5,
0413     event_index___release_mem__shader_done = 6
0414 };
0415
0416 enum RELEASE_MEM_cache_policy_enum {
0417     cache_policy___release_mem__lru = 0,
0418     cache_policy___release_mem__stream = 1,
0419     cache_policy___release_mem__bypass = 2
0420 };
0421
0422 enum RELEASE_MEM_dst_sel_enum {
0423     dst_sel___release_mem__memory_controller = 0,
0424     dst_sel___release_mem__tc_l2 = 1,
0425     dst_sel___release_mem__queue_write_pointer_register = 2,
0426     dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3
0427 };
0428
0429 enum RELEASE_MEM_int_sel_enum {
0430     int_sel___release_mem__none = 0,
0431     int_sel___release_mem__send_interrupt_only = 1,
0432     int_sel___release_mem__send_interrupt_after_write_confirm = 2,
0433     int_sel___release_mem__send_data_after_write_confirm = 3
0434 };
0435
0436 enum RELEASE_MEM_data_sel_enum {
0437     data_sel___release_mem__none = 0,
0438     data_sel___release_mem__send_32_bit_low = 1,
0439     data_sel___release_mem__send_64_bit_data = 2,
0440     data_sel___release_mem__send_gpu_clock_counter = 3,
0441     data_sel___release_mem__send_cp_perfcounter_hi_lo = 4,
0442     data_sel___release_mem__store_gds_data_to_memory = 5
0443 };
0444
0445 struct pm4_mec_release_mem {
0446     union {
0447         union PM4_MES_TYPE_3_HEADER header;     /*header */
0448         unsigned int ordinal1;
0449     };
0450
0451     union {
0452         struct {
0453             unsigned int event_type:6;
0454             unsigned int reserved1:2;
0455             enum RELEASE_MEM_event_index_enum event_index:4;
0456             unsigned int tcl1_vol_action_ena:1;
0457             unsigned int tc_vol_action_ena:1;
0458             unsigned int reserved2:1;
0459             unsigned int tc_wb_action_ena:1;
0460             unsigned int tcl1_action_ena:1;
0461             unsigned int tc_action_ena:1;
0462             unsigned int reserved3:6;
0463             unsigned int atc:1;
0464             enum RELEASE_MEM_cache_policy_enum cache_policy:2;
0465             unsigned int reserved4:5;
0466         } bitfields2;
0467         unsigned int ordinal2;
0468     };
0469
0470     union {
0471         struct {
0472             unsigned int reserved5:16;
0473             enum RELEASE_MEM_dst_sel_enum dst_sel:2;
0474             unsigned int reserved6:6;
0475             enum RELEASE_MEM_int_sel_enum int_sel:3;
0476             unsigned int reserved7:2;
0477             enum RELEASE_MEM_data_sel_enum data_sel:3;
0478         } bitfields3;
0479         unsigned int ordinal3;
0480     };
0481
0482     union {
0483         struct {
0484             unsigned int reserved8:2;
0485             unsigned int address_lo_32b:30;
0486         } bitfields4;
0487         struct {
0488             unsigned int reserved9:3;
0489             unsigned int address_lo_64b:29;
0490         } bitfields5;
0491         unsigned int ordinal4;
0492     };
0493
0494     unsigned int address_hi;
0495
0496     unsigned int data_lo;
0497
0498     unsigned int data_hi;
0499 };
0500 #endif
0501
0502 enum {
0503     CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
0504 };
0505
0506 #endif