amd/amdkfd/kfd_pm4_headers_diq.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
0002 /*
0003  * Copyright 2014-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #ifndef KFD_PM4_HEADERS_DIQ_H_
0026 #define KFD_PM4_HEADERS_DIQ_H_
0027
0028 /*--------------------_INDIRECT_BUFFER-------------------- */
0029
0030 #ifndef _PM4__INDIRECT_BUFFER_DEFINED
0031 #define _PM4__INDIRECT_BUFFER_DEFINED
0032 enum _INDIRECT_BUFFER_cache_policy_enum {
0033     cache_policy___indirect_buffer__lru = 0,
0034     cache_policy___indirect_buffer__stream = 1,
0035     cache_policy___indirect_buffer__bypass = 2
0036 };
0037
0038 enum {
0039     IT_INDIRECT_BUFFER_PASID = 0x5C
0040 };
0041
0042 struct pm4__indirect_buffer_pasid {
0043     union {
0044         union PM4_MES_TYPE_3_HEADER header; /* header */
0045         unsigned int ordinal1;
0046     };
0047
0048     union {
0049         struct {
0050             unsigned int reserved1:2;
0051             unsigned int ib_base_lo:30;
0052         } bitfields2;
0053         unsigned int ordinal2;
0054     };
0055
0056     union {
0057         struct {
0058             unsigned int ib_base_hi:16;
0059             unsigned int reserved2:16;
0060         } bitfields3;
0061         unsigned int ordinal3;
0062     };
0063
0064     union {
0065         unsigned int control;
0066         unsigned int ordinal4;
0067     };
0068
0069     union {
0070         struct {
0071             unsigned int pasid:10;
0072             unsigned int reserved4:22;
0073         } bitfields5;
0074         unsigned int ordinal5;
0075     };
0076
0077 };
0078
0079 #endif
0080
0081 /*--------------------_RELEASE_MEM-------------------- */
0082
0083 #ifndef _PM4__RELEASE_MEM_DEFINED
0084 #define _PM4__RELEASE_MEM_DEFINED
0085 enum _RELEASE_MEM_event_index_enum {
0086     event_index___release_mem__end_of_pipe = 5,
0087     event_index___release_mem__shader_done = 6
0088 };
0089
0090 enum _RELEASE_MEM_cache_policy_enum {
0091     cache_policy___release_mem__lru = 0,
0092     cache_policy___release_mem__stream = 1,
0093     cache_policy___release_mem__bypass = 2
0094 };
0095
0096 enum _RELEASE_MEM_dst_sel_enum {
0097     dst_sel___release_mem__memory_controller = 0,
0098     dst_sel___release_mem__tc_l2 = 1,
0099     dst_sel___release_mem__queue_write_pointer_register = 2,
0100     dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3
0101 };
0102
0103 enum _RELEASE_MEM_int_sel_enum {
0104     int_sel___release_mem__none = 0,
0105     int_sel___release_mem__send_interrupt_only = 1,
0106     int_sel___release_mem__send_interrupt_after_write_confirm = 2,
0107     int_sel___release_mem__send_data_after_write_confirm = 3
0108 };
0109
0110 enum _RELEASE_MEM_data_sel_enum {
0111     data_sel___release_mem__none = 0,
0112     data_sel___release_mem__send_32_bit_low = 1,
0113     data_sel___release_mem__send_64_bit_data = 2,
0114     data_sel___release_mem__send_gpu_clock_counter = 3,
0115     data_sel___release_mem__send_cp_perfcounter_hi_lo = 4,
0116     data_sel___release_mem__store_gds_data_to_memory = 5
0117 };
0118
0119 struct pm4__release_mem {
0120     union {
0121         union PM4_MES_TYPE_3_HEADER header; /*header */
0122         unsigned int ordinal1;
0123     };
0124
0125     union {
0126         struct {
0127             unsigned int event_type:6;
0128             unsigned int reserved1:2;
0129             enum _RELEASE_MEM_event_index_enum event_index:4;
0130             unsigned int tcl1_vol_action_ena:1;
0131             unsigned int tc_vol_action_ena:1;
0132             unsigned int reserved2:1;
0133             unsigned int tc_wb_action_ena:1;
0134             unsigned int tcl1_action_ena:1;
0135             unsigned int tc_action_ena:1;
0136             unsigned int reserved3:6;
0137             unsigned int atc:1;
0138             enum _RELEASE_MEM_cache_policy_enum cache_policy:2;
0139             unsigned int reserved4:5;
0140         } bitfields2;
0141         unsigned int ordinal2;
0142     };
0143
0144     union {
0145         struct {
0146             unsigned int reserved5:16;
0147             enum _RELEASE_MEM_dst_sel_enum dst_sel:2;
0148             unsigned int reserved6:6;
0149             enum _RELEASE_MEM_int_sel_enum int_sel:3;
0150             unsigned int reserved7:2;
0151             enum _RELEASE_MEM_data_sel_enum data_sel:3;
0152         } bitfields3;
0153         unsigned int ordinal3;
0154     };
0155
0156     union {
0157         struct {
0158             unsigned int reserved8:2;
0159             unsigned int address_lo_32b:30;
0160         } bitfields4;
0161         struct {
0162             unsigned int reserved9:3;
0163             unsigned int address_lo_64b:29;
0164         } bitfields5;
0165         unsigned int ordinal4;
0166     };
0167
0168     unsigned int address_hi;
0169
0170     unsigned int data_lo;
0171
0172     unsigned int data_hi;
0173
0174 };
0175 #endif
0176
0177
0178 /*--------------------_SET_CONFIG_REG-------------------- */
0179
0180 #ifndef _PM4__SET_CONFIG_REG_DEFINED
0181 #define _PM4__SET_CONFIG_REG_DEFINED
0182
0183 struct pm4__set_config_reg {
0184     union {
0185         union PM4_MES_TYPE_3_HEADER header; /*header */
0186         unsigned int ordinal1;
0187     };
0188
0189     union {
0190         struct {
0191             unsigned int reg_offset:16;
0192             unsigned int reserved1:7;
0193             unsigned int vmid_shift:5;
0194             unsigned int insert_vmid:1;
0195             unsigned int reserved2:3;
0196         } bitfields2;
0197         unsigned int ordinal2;
0198     };
0199
0200     unsigned int reg_data[1];   /*1..N of these fields */
0201
0202 };
0203 #endif
0204
0205 /*--------------------_WAIT_REG_MEM-------------------- */
0206
0207 #ifndef _PM4__WAIT_REG_MEM_DEFINED
0208 #define _PM4__WAIT_REG_MEM_DEFINED
0209 enum _WAIT_REG_MEM_function_enum {
0210     function___wait_reg_mem__always_pass = 0,
0211     function___wait_reg_mem__less_than_ref_value = 1,
0212     function___wait_reg_mem__less_than_equal_to_the_ref_value = 2,
0213     function___wait_reg_mem__equal_to_the_reference_value = 3,
0214     function___wait_reg_mem__not_equal_reference_value = 4,
0215     function___wait_reg_mem__greater_than_or_equal_reference_value = 5,
0216     function___wait_reg_mem__greater_than_reference_value = 6,
0217     function___wait_reg_mem__reserved = 7
0218 };
0219
0220 enum _WAIT_REG_MEM_mem_space_enum {
0221     mem_space___wait_reg_mem__register_space = 0,
0222     mem_space___wait_reg_mem__memory_space = 1
0223 };
0224
0225 enum _WAIT_REG_MEM_operation_enum {
0226     operation___wait_reg_mem__wait_reg_mem = 0,
0227     operation___wait_reg_mem__wr_wait_wr_reg = 1
0228 };
0229
0230 struct pm4__wait_reg_mem {
0231     union {
0232         union PM4_MES_TYPE_3_HEADER header; /*header */
0233         unsigned int ordinal1;
0234     };
0235
0236     union {
0237         struct {
0238             enum _WAIT_REG_MEM_function_enum function:3;
0239             unsigned int reserved1:1;
0240             enum _WAIT_REG_MEM_mem_space_enum mem_space:2;
0241             enum _WAIT_REG_MEM_operation_enum operation:2;
0242             unsigned int reserved2:24;
0243         } bitfields2;
0244         unsigned int ordinal2;
0245     };
0246
0247     union {
0248         struct {
0249             unsigned int reserved3:2;
0250             unsigned int memory_poll_addr_lo:30;
0251         } bitfields3;
0252         struct {
0253             unsigned int register_poll_addr:16;
0254             unsigned int reserved4:16;
0255         } bitfields4;
0256         struct {
0257             unsigned int register_write_addr:16;
0258             unsigned int reserved5:16;
0259         } bitfields5;
0260         unsigned int ordinal3;
0261     };
0262
0263     union {
0264         struct {
0265             unsigned int poll_address_hi:16;
0266             unsigned int reserved6:16;
0267         } bitfields6;
0268         struct {
0269             unsigned int register_write_addr:16;
0270             unsigned int reserved7:16;
0271         } bitfields7;
0272         unsigned int ordinal4;
0273     };
0274
0275     unsigned int reference;
0276
0277     unsigned int mask;
0278
0279     union {
0280         struct {
0281             unsigned int poll_interval:16;
0282             unsigned int reserved8:16;
0283         } bitfields8;
0284         unsigned int ordinal7;
0285     };
0286
0287 };
0288 #endif
0289
0290
0291 #endif /* KFD_PM4_HEADERS_DIQ_H_ */