amd/amdkfd/kfd_pm4_headers_aldebaran.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
0002 /*
0003  * Copyright 2020-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 /*--------------------MES_MAP_PROCESS (PER DEBUG VMID)--------------------*/
0026
0027 #ifndef PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
0028 #define PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
0029
0030 struct pm4_mes_map_process_aldebaran {
0031     union {
0032         union PM4_MES_TYPE_3_HEADER header; /* header */
0033         uint32_t ordinal1;
0034     };
0035
0036     union {
0037         struct {
0038             uint32_t pasid:16;      /* 0 - 15  */
0039             uint32_t single_memops:1;   /* 16      */
0040             uint32_t reserved1:1;       /* 17      */
0041             uint32_t debug_vmid:4;      /* 18 - 21 */
0042             uint32_t new_debug:1;       /* 22      */
0043             uint32_t tmz:1;         /* 23      */
0044             uint32_t diq_enable:1;      /* 24      */
0045             uint32_t process_quantum:7; /* 25 - 31 */
0046         } bitfields2;
0047         uint32_t ordinal2;
0048     };
0049
0050     uint32_t vm_context_page_table_base_addr_lo32;
0051
0052     uint32_t vm_context_page_table_base_addr_hi32;
0053
0054     uint32_t sh_mem_bases;
0055
0056     uint32_t sh_mem_config;
0057
0058     uint32_t sq_shader_tba_lo;
0059
0060     uint32_t sq_shader_tba_hi;
0061
0062     uint32_t sq_shader_tma_lo;
0063
0064     uint32_t sq_shader_tma_hi;
0065
0066     uint32_t reserved6;
0067
0068     uint32_t gds_addr_lo;
0069
0070     uint32_t gds_addr_hi;
0071
0072     union {
0073         struct {
0074             uint32_t num_gws:7;
0075             uint32_t sdma_enable:1;
0076             uint32_t num_oac:4;
0077             uint32_t gds_size_hi:4;
0078             uint32_t gds_size:6;
0079             uint32_t num_queues:10;
0080         } bitfields14;
0081         uint32_t ordinal14;
0082     };
0083
0084     uint32_t spi_gdbg_per_vmid_cntl;
0085
0086     uint32_t tcp_watch_cntl[4];
0087
0088     uint32_t completion_signal_lo;
0089
0090     uint32_t completion_signal_hi;
0091
0092 };
0093
0094 #endif