amd/amdkfd/kfd_pm4_headers_ai.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
0002 /*
0003  * Copyright 2016-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #ifndef F32_MES_PM4_PACKETS_H
0026 #define F32_MES_PM4_PACKETS_H
0027
0028 #ifndef PM4_MES_HEADER_DEFINED
0029 #define PM4_MES_HEADER_DEFINED
0030 union PM4_MES_TYPE_3_HEADER {
0031     struct {
0032         uint32_t reserved1 : 8; /* < reserved */
0033         uint32_t opcode    : 8; /* < IT opcode */
0034         uint32_t count     : 14;/* < number of DWORDs - 1 in the
0035                      *   information body.
0036                      */
0037         uint32_t type      : 2; /* < packet identifier.
0038                      *   It should be 3 for type 3 packets
0039                      */
0040     };
0041     uint32_t u32All;
0042 };
0043 #endif /* PM4_MES_HEADER_DEFINED */
0044
0045 /*--------------------MES_SET_RESOURCES--------------------*/
0046
0047 #ifndef PM4_MES_SET_RESOURCES_DEFINED
0048 #define PM4_MES_SET_RESOURCES_DEFINED
0049 enum mes_set_resources_queue_type_enum {
0050     queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
0051     queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
0052     queue_type__mes_set_resources__hsa_debug_interface_queue = 4
0053 };
0054
0055
0056 struct pm4_mes_set_resources {
0057     union {
0058         union PM4_MES_TYPE_3_HEADER header;     /* header */
0059         uint32_t            ordinal1;
0060     };
0061
0062     union {
0063         struct {
0064             uint32_t vmid_mask:16;
0065             uint32_t unmap_latency:8;
0066             uint32_t reserved1:5;
0067             enum mes_set_resources_queue_type_enum queue_type:3;
0068         } bitfields2;
0069         uint32_t ordinal2;
0070     };
0071
0072     uint32_t queue_mask_lo;
0073     uint32_t queue_mask_hi;
0074     uint32_t gws_mask_lo;
0075     uint32_t gws_mask_hi;
0076
0077     union {
0078         struct {
0079             uint32_t oac_mask:16;
0080             uint32_t reserved2:16;
0081         } bitfields7;
0082         uint32_t ordinal7;
0083     };
0084
0085     union {
0086         struct {
0087         uint32_t gds_heap_base:10;
0088         uint32_t reserved3:1;
0089         uint32_t gds_heap_size:10;
0090         uint32_t reserved4:11;
0091         } bitfields8;
0092         uint32_t ordinal8;
0093     };
0094
0095 };
0096 #endif
0097
0098 /*--------------------MES_RUN_LIST--------------------*/
0099
0100 #ifndef PM4_MES_RUN_LIST_DEFINED
0101 #define PM4_MES_RUN_LIST_DEFINED
0102
0103 struct pm4_mes_runlist {
0104     union {
0105         union PM4_MES_TYPE_3_HEADER header; /* header */
0106         uint32_t ordinal1;
0107     };
0108
0109     union {
0110         struct {
0111             uint32_t reserved1:2;
0112             uint32_t ib_base_lo:30;
0113         } bitfields2;
0114         uint32_t ordinal2;
0115     };
0116
0117     uint32_t ib_base_hi;
0118
0119     union {
0120         struct {
0121             uint32_t ib_size:20;
0122             uint32_t chain:1;
0123             uint32_t offload_polling:1;
0124             uint32_t chained_runlist_idle_disable:1;
0125             uint32_t valid:1;
0126             uint32_t process_cnt:4;
0127             uint32_t reserved3:4;
0128         } bitfields4;
0129         uint32_t ordinal4;
0130     };
0131
0132 };
0133 #endif
0134
0135 /*--------------------MES_MAP_PROCESS--------------------*/
0136
0137 #ifndef PM4_MES_MAP_PROCESS_DEFINED
0138 #define PM4_MES_MAP_PROCESS_DEFINED
0139
0140 struct pm4_mes_map_process {
0141     union {
0142         union PM4_MES_TYPE_3_HEADER header; /* header */
0143         uint32_t ordinal1;
0144     };
0145
0146     union {
0147         struct {
0148             uint32_t pasid:16;
0149             uint32_t reserved1:8;
0150             uint32_t diq_enable:1;
0151             uint32_t process_quantum:7;
0152         } bitfields2;
0153         uint32_t ordinal2;
0154     };
0155
0156     uint32_t vm_context_page_table_base_addr_lo32;
0157
0158     uint32_t vm_context_page_table_base_addr_hi32;
0159
0160     uint32_t sh_mem_bases;
0161
0162     uint32_t sh_mem_config;
0163
0164     uint32_t sq_shader_tba_lo;
0165
0166     uint32_t sq_shader_tba_hi;
0167
0168     uint32_t sq_shader_tma_lo;
0169
0170     uint32_t sq_shader_tma_hi;
0171
0172     uint32_t reserved6;
0173
0174     uint32_t gds_addr_lo;
0175
0176     uint32_t gds_addr_hi;
0177
0178     union {
0179         struct {
0180             uint32_t num_gws:7;
0181             uint32_t sdma_enable:1;
0182             uint32_t num_oac:4;
0183             uint32_t gds_size_hi:4;
0184             uint32_t gds_size:6;
0185             uint32_t num_queues:10;
0186         } bitfields14;
0187         uint32_t ordinal14;
0188     };
0189
0190     uint32_t completion_signal_lo;
0191
0192     uint32_t completion_signal_hi;
0193
0194 };
0195
0196 #endif
0197
0198 /*--------------------MES_MAP_PROCESS_VM--------------------*/
0199
0200 #ifndef PM4_MES_MAP_PROCESS_VM_DEFINED
0201 #define PM4_MES_MAP_PROCESS_VM_DEFINED
0202
0203 struct PM4_MES_MAP_PROCESS_VM {
0204     union {
0205         union PM4_MES_TYPE_3_HEADER header; /* header */
0206         uint32_t ordinal1;
0207     };
0208
0209     uint32_t reserved1;
0210
0211     uint32_t vm_context_cntl;
0212
0213     uint32_t reserved2;
0214
0215     uint32_t vm_context_page_table_end_addr_lo32;
0216
0217     uint32_t vm_context_page_table_end_addr_hi32;
0218
0219     uint32_t vm_context_page_table_start_addr_lo32;
0220
0221     uint32_t vm_context_page_table_start_addr_hi32;
0222
0223     uint32_t reserved3;
0224
0225     uint32_t reserved4;
0226
0227     uint32_t reserved5;
0228
0229     uint32_t reserved6;
0230
0231     uint32_t reserved7;
0232
0233     uint32_t reserved8;
0234
0235     uint32_t completion_signal_lo32;
0236
0237     uint32_t completion_signal_hi32;
0238
0239 };
0240 #endif
0241
0242 /*--------------------MES_MAP_QUEUES--------------------*/
0243
0244 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
0245 #define PM4_MES_MAP_QUEUES_VI_DEFINED
0246 enum mes_map_queues_queue_sel_enum {
0247     queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
0248 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
0249 };
0250
0251 enum mes_map_queues_queue_type_enum {
0252     queue_type__mes_map_queues__normal_compute_vi = 0,
0253     queue_type__mes_map_queues__debug_interface_queue_vi = 1,
0254     queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
0255 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
0256 };
0257
0258 enum mes_map_queues_engine_sel_enum {
0259     engine_sel__mes_map_queues__compute_vi = 0,
0260     engine_sel__mes_map_queues__sdma0_vi = 2,
0261     engine_sel__mes_map_queues__sdma1_vi = 3
0262 };
0263
0264 enum mes_map_queues_extended_engine_sel_enum {
0265     extended_engine_sel__mes_map_queues__legacy_engine_sel = 0,
0266     extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1
0267 };
0268
0269 struct pm4_mes_map_queues {
0270     union {
0271         union PM4_MES_TYPE_3_HEADER   header;            /* header */
0272         uint32_t            ordinal1;
0273     };
0274
0275     union {
0276         struct {
0277             uint32_t reserved1:2;
0278             enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2;
0279             enum mes_map_queues_queue_sel_enum queue_sel:2;
0280             uint32_t reserved5:6;
0281             uint32_t gws_control_queue:1;
0282             uint32_t reserved2:8;
0283             enum mes_map_queues_queue_type_enum queue_type:3;
0284             uint32_t reserved3:2;
0285             enum mes_map_queues_engine_sel_enum engine_sel:3;
0286             uint32_t num_queues:3;
0287         } bitfields2;
0288         uint32_t ordinal2;
0289     };
0290
0291     union {
0292         struct {
0293             uint32_t reserved3:1;
0294             uint32_t check_disable:1;
0295             uint32_t doorbell_offset:26;
0296             uint32_t reserved4:4;
0297         } bitfields3;
0298         uint32_t ordinal3;
0299     };
0300
0301     uint32_t mqd_addr_lo;
0302     uint32_t mqd_addr_hi;
0303     uint32_t wptr_addr_lo;
0304     uint32_t wptr_addr_hi;
0305 };
0306 #endif
0307
0308 /*--------------------MES_QUERY_STATUS--------------------*/
0309
0310 #ifndef PM4_MES_QUERY_STATUS_DEFINED
0311 #define PM4_MES_QUERY_STATUS_DEFINED
0312 enum mes_query_status_interrupt_sel_enum {
0313     interrupt_sel__mes_query_status__completion_status = 0,
0314     interrupt_sel__mes_query_status__process_status = 1,
0315     interrupt_sel__mes_query_status__queue_status = 2
0316 };
0317
0318 enum mes_query_status_command_enum {
0319     command__mes_query_status__interrupt_only = 0,
0320     command__mes_query_status__fence_only_immediate = 1,
0321     command__mes_query_status__fence_only_after_write_ack = 2,
0322     command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
0323 };
0324
0325 enum mes_query_status_engine_sel_enum {
0326     engine_sel__mes_query_status__compute = 0,
0327     engine_sel__mes_query_status__sdma0_queue = 2,
0328     engine_sel__mes_query_status__sdma1_queue = 3
0329 };
0330
0331 struct pm4_mes_query_status {
0332     union {
0333         union PM4_MES_TYPE_3_HEADER   header;            /* header */
0334         uint32_t            ordinal1;
0335     };
0336
0337     union {
0338         struct {
0339             uint32_t context_id:28;
0340             enum mes_query_status_interrupt_sel_enum    interrupt_sel:2;
0341             enum mes_query_status_command_enum command:2;
0342         } bitfields2;
0343         uint32_t ordinal2;
0344     };
0345
0346     union {
0347         struct {
0348             uint32_t pasid:16;
0349             uint32_t reserved1:16;
0350         } bitfields3a;
0351         struct {
0352             uint32_t reserved2:2;
0353             uint32_t doorbell_offset:26;
0354             enum mes_query_status_engine_sel_enum engine_sel:3;
0355             uint32_t reserved3:1;
0356         } bitfields3b;
0357         uint32_t ordinal3;
0358     };
0359
0360     uint32_t addr_lo;
0361     uint32_t addr_hi;
0362     uint32_t data_lo;
0363     uint32_t data_hi;
0364 };
0365 #endif
0366
0367 /*--------------------MES_UNMAP_QUEUES--------------------*/
0368
0369 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED
0370 #define PM4_MES_UNMAP_QUEUES_DEFINED
0371 enum mes_unmap_queues_action_enum {
0372     action__mes_unmap_queues__preempt_queues = 0,
0373     action__mes_unmap_queues__reset_queues = 1,
0374     action__mes_unmap_queues__disable_process_queues = 2,
0375     action__mes_unmap_queues__reserved = 3
0376 };
0377
0378 enum mes_unmap_queues_queue_sel_enum {
0379     queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
0380     queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
0381     queue_sel__mes_unmap_queues__unmap_all_queues = 2,
0382     queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
0383 };
0384
0385 enum mes_unmap_queues_engine_sel_enum {
0386     engine_sel__mes_unmap_queues__compute = 0,
0387     engine_sel__mes_unmap_queues__sdma0 = 2,
0388     engine_sel__mes_unmap_queues__sdmal = 3
0389 };
0390
0391 enum mes_unmap_queues_extended_engine_sel_enum {
0392     extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0,
0393     extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1
0394 };
0395
0396 struct pm4_mes_unmap_queues {
0397     union {
0398         union PM4_MES_TYPE_3_HEADER   header;            /* header */
0399         uint32_t            ordinal1;
0400     };
0401
0402     union {
0403         struct {
0404             enum mes_unmap_queues_action_enum action:2;
0405             enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2;
0406             enum mes_unmap_queues_queue_sel_enum queue_sel:2;
0407             uint32_t reserved2:20;
0408             enum mes_unmap_queues_engine_sel_enum engine_sel:3;
0409             uint32_t num_queues:3;
0410         } bitfields2;
0411         uint32_t ordinal2;
0412     };
0413
0414     union {
0415         struct {
0416             uint32_t pasid:16;
0417             uint32_t reserved3:16;
0418         } bitfields3a;
0419         struct {
0420             uint32_t reserved4:2;
0421             uint32_t doorbell_offset0:26;
0422             int32_t reserved5:4;
0423         } bitfields3b;
0424         uint32_t ordinal3;
0425     };
0426
0427     union {
0428     struct {
0429             uint32_t reserved6:2;
0430             uint32_t doorbell_offset1:26;
0431             uint32_t reserved7:4;
0432         } bitfields4;
0433         uint32_t ordinal4;
0434     };
0435
0436     union {
0437         struct {
0438             uint32_t reserved8:2;
0439             uint32_t doorbell_offset2:26;
0440             uint32_t reserved9:4;
0441         } bitfields5;
0442         uint32_t ordinal5;
0443     };
0444
0445     union {
0446         struct {
0447             uint32_t reserved10:2;
0448             uint32_t doorbell_offset3:26;
0449             uint32_t reserved11:4;
0450         } bitfields6;
0451         uint32_t ordinal6;
0452     };
0453 };
0454 #endif
0455
0456 #ifndef PM4_MEC_RELEASE_MEM_DEFINED
0457 #define PM4_MEC_RELEASE_MEM_DEFINED
0458
0459 enum mec_release_mem_event_index_enum {
0460     event_index__mec_release_mem__end_of_pipe = 5,
0461     event_index__mec_release_mem__shader_done = 6
0462 };
0463
0464 enum mec_release_mem_cache_policy_enum {
0465     cache_policy__mec_release_mem__lru = 0,
0466     cache_policy__mec_release_mem__stream = 1
0467 };
0468
0469 enum mec_release_mem_pq_exe_status_enum {
0470     pq_exe_status__mec_release_mem__default = 0,
0471     pq_exe_status__mec_release_mem__phase_update = 1
0472 };
0473
0474 enum mec_release_mem_dst_sel_enum {
0475     dst_sel__mec_release_mem__memory_controller = 0,
0476     dst_sel__mec_release_mem__tc_l2 = 1,
0477     dst_sel__mec_release_mem__queue_write_pointer_register = 2,
0478     dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3
0479 };
0480
0481 enum mec_release_mem_int_sel_enum {
0482     int_sel__mec_release_mem__none = 0,
0483     int_sel__mec_release_mem__send_interrupt_only = 1,
0484     int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2,
0485     int_sel__mec_release_mem__send_data_after_write_confirm = 3,
0486     int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4,
0487     int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5,
0488     int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6
0489 };
0490
0491 enum mec_release_mem_data_sel_enum {
0492     data_sel__mec_release_mem__none = 0,
0493     data_sel__mec_release_mem__send_32_bit_low = 1,
0494     data_sel__mec_release_mem__send_64_bit_data = 2,
0495     data_sel__mec_release_mem__send_gpu_clock_counter = 3,
0496     data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4,
0497     data_sel__mec_release_mem__store_gds_data_to_memory = 5
0498 };
0499
0500 struct pm4_mec_release_mem {
0501     union {
0502         union PM4_MES_TYPE_3_HEADER header;     /*header */
0503         unsigned int ordinal1;
0504     };
0505
0506     union {
0507         struct {
0508             unsigned int event_type:6;
0509             unsigned int reserved1:2;
0510             enum mec_release_mem_event_index_enum event_index:4;
0511             unsigned int tcl1_vol_action_ena:1;
0512             unsigned int tc_vol_action_ena:1;
0513             unsigned int reserved2:1;
0514             unsigned int tc_wb_action_ena:1;
0515             unsigned int tcl1_action_ena:1;
0516             unsigned int tc_action_ena:1;
0517             uint32_t reserved3:1;
0518             uint32_t tc_nc_action_ena:1;
0519             uint32_t tc_wc_action_ena:1;
0520             uint32_t tc_md_action_ena:1;
0521             uint32_t reserved4:3;
0522             enum mec_release_mem_cache_policy_enum cache_policy:2;
0523             uint32_t reserved5:2;
0524             enum mec_release_mem_pq_exe_status_enum pq_exe_status:1;
0525             uint32_t reserved6:2;
0526         } bitfields2;
0527         unsigned int ordinal2;
0528     };
0529
0530     union {
0531         struct {
0532             uint32_t reserved7:16;
0533             enum mec_release_mem_dst_sel_enum dst_sel:2;
0534             uint32_t reserved8:6;
0535             enum mec_release_mem_int_sel_enum int_sel:3;
0536             uint32_t reserved9:2;
0537             enum mec_release_mem_data_sel_enum data_sel:3;
0538         } bitfields3;
0539         unsigned int ordinal3;
0540     };
0541
0542     union {
0543         struct {
0544             uint32_t reserved10:2;
0545             unsigned int address_lo_32b:30;
0546         } bitfields4;
0547         struct {
0548             uint32_t reserved11:3;
0549             uint32_t address_lo_64b:29;
0550         } bitfields4b;
0551         uint32_t reserved12;
0552         unsigned int ordinal4;
0553     };
0554
0555     union {
0556         uint32_t address_hi;
0557         uint32_t reserved13;
0558         uint32_t ordinal5;
0559     };
0560
0561     union {
0562         uint32_t data_lo;
0563         uint32_t cmp_data_lo;
0564         struct {
0565             uint32_t dw_offset:16;
0566             uint32_t num_dwords:16;
0567         } bitfields6c;
0568         uint32_t reserved14;
0569         uint32_t ordinal6;
0570     };
0571
0572     union {
0573         uint32_t data_hi;
0574         uint32_t cmp_data_hi;
0575         uint32_t reserved15;
0576         uint32_t reserved16;
0577         uint32_t ordinal7;
0578     };
0579
0580     uint32_t int_ctxid;
0581
0582 };
0583
0584 #endif
0585
0586 enum {
0587     CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
0588 };
0589 #endif
0590