amd/amdkfd/kfd_pm4_headers.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
0002 /*
0003  * Copyright 2014-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #ifndef KFD_PM4_HEADERS_H_
0026 #define KFD_PM4_HEADERS_H_
0027
0028 #ifndef PM4_MES_HEADER_DEFINED
0029 #define PM4_MES_HEADER_DEFINED
0030 union PM4_MES_TYPE_3_HEADER {
0031     struct {
0032         /* reserved */
0033         uint32_t reserved1:8;
0034         /* IT opcode */
0035         uint32_t opcode:8;
0036         /* number of DWORDs - 1 in the information body */
0037         uint32_t count:14;
0038         /* packet identifier. It should be 3 for type 3 packets */
0039         uint32_t type:2;
0040     };
0041     uint32_t u32all;
0042 };
0043 #endif /* PM4_MES_HEADER_DEFINED */
0044
0045
0046 /*--------------------MES_MAP_PROCESS-------------------- */
0047
0048 #ifndef PM4_MES_MAP_PROCESS_DEFINED
0049 #define PM4_MES_MAP_PROCESS_DEFINED
0050
0051 struct pm4_map_process {
0052     union {
0053         union PM4_MES_TYPE_3_HEADER header; /* header */
0054         uint32_t ordinal1;
0055     };
0056
0057     union {
0058         struct {
0059             uint32_t pasid:16;
0060             uint32_t reserved1:8;
0061             uint32_t diq_enable:1;
0062             uint32_t process_quantum:7;
0063         } bitfields2;
0064         uint32_t ordinal2;
0065     };
0066
0067     union {
0068         struct {
0069             uint32_t page_table_base:28;
0070             uint32_t reserved3:4;
0071         } bitfields3;
0072         uint32_t ordinal3;
0073     };
0074
0075     uint32_t sh_mem_bases;
0076     uint32_t sh_mem_ape1_base;
0077     uint32_t sh_mem_ape1_limit;
0078     uint32_t sh_mem_config;
0079     uint32_t gds_addr_lo;
0080     uint32_t gds_addr_hi;
0081
0082     union {
0083         struct {
0084             uint32_t num_gws:6;
0085             uint32_t reserved4:2;
0086             uint32_t num_oac:4;
0087             uint32_t reserved5:4;
0088             uint32_t gds_size:6;
0089             uint32_t num_queues:10;
0090         } bitfields10;
0091         uint32_t ordinal10;
0092     };
0093
0094 };
0095 #endif
0096
0097 #ifndef PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
0098 #define PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
0099
0100 struct pm4_map_process_scratch_kv {
0101     union {
0102         union PM4_MES_TYPE_3_HEADER   header; /* header */
0103         uint32_t            ordinal1;
0104     };
0105
0106     union {
0107         struct {
0108             uint32_t pasid:16;
0109             uint32_t reserved1:8;
0110             uint32_t diq_enable:1;
0111             uint32_t process_quantum:7;
0112         } bitfields2;
0113         uint32_t ordinal2;
0114     };
0115
0116     union {
0117         struct {
0118             uint32_t page_table_base:28;
0119             uint32_t reserved2:4;
0120         } bitfields3;
0121         uint32_t ordinal3;
0122     };
0123
0124     uint32_t reserved3;
0125     uint32_t sh_mem_bases;
0126     uint32_t sh_mem_config;
0127     uint32_t sh_mem_ape1_base;
0128     uint32_t sh_mem_ape1_limit;
0129     uint32_t sh_hidden_private_base_vmid;
0130     uint32_t reserved4;
0131     uint32_t reserved5;
0132     uint32_t gds_addr_lo;
0133     uint32_t gds_addr_hi;
0134
0135     union {
0136         struct {
0137             uint32_t num_gws:6;
0138             uint32_t reserved6:2;
0139             uint32_t num_oac:4;
0140             uint32_t reserved7:4;
0141             uint32_t gds_size:6;
0142             uint32_t num_queues:10;
0143         } bitfields14;
0144         uint32_t ordinal14;
0145     };
0146
0147     uint32_t completion_signal_lo32;
0148 uint32_t completion_signal_hi32;
0149 };
0150 #endif
0151
0152 enum {
0153     CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
0154 };
0155
0156 #endif /* KFD_PM4_HEADERS_H_ */