amd/amdkfd/kfd_packet_manager_vi.c

0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * Copyright 2014-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #include "kfd_kernel_queue.h"
0026 #include "kfd_device_queue_manager.h"
0027 #include "kfd_pm4_headers_vi.h"
0028 #include "kfd_pm4_opcodes.h"
0029
0030 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size)
0031 {
0032     union PM4_MES_TYPE_3_HEADER header;
0033
0034     header.u32All = 0;
0035     header.opcode = opcode;
0036     header.count = packet_size / 4 - 2;
0037     header.type = PM4_TYPE_3;
0038
0039     return header.u32All;
0040 }
0041
0042 static int pm_map_process_vi(struct packet_manager *pm, uint32_t *buffer,
0043                 struct qcm_process_device *qpd)
0044 {
0045     struct pm4_mes_map_process *packet;
0046
0047     packet = (struct pm4_mes_map_process *)buffer;
0048
0049     memset(buffer, 0, sizeof(struct pm4_mes_map_process));
0050
0051     packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
0052                     sizeof(struct pm4_mes_map_process));
0053     packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
0054     packet->bitfields2.process_quantum = 10;
0055     packet->bitfields2.pasid = qpd->pqm->process->pasid;
0056     packet->bitfields3.page_table_base = qpd->page_table_base;
0057     packet->bitfields10.gds_size = qpd->gds_size;
0058     packet->bitfields10.num_gws = qpd->num_gws;
0059     packet->bitfields10.num_oac = qpd->num_oac;
0060     packet->bitfields10.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
0061
0062     packet->sh_mem_config = qpd->sh_mem_config;
0063     packet->sh_mem_bases = qpd->sh_mem_bases;
0064     packet->sh_mem_ape1_base = qpd->sh_mem_ape1_base;
0065     packet->sh_mem_ape1_limit = qpd->sh_mem_ape1_limit;
0066
0067     packet->sh_hidden_private_base_vmid = qpd->sh_hidden_private_base;
0068
0069     packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
0070     packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
0071
0072     return 0;
0073 }
0074
0075 static int pm_runlist_vi(struct packet_manager *pm, uint32_t *buffer,
0076             uint64_t ib, size_t ib_size_in_dwords, bool chain)
0077 {
0078     struct pm4_mes_runlist *packet;
0079     int concurrent_proc_cnt = 0;
0080     struct kfd_dev *kfd = pm->dqm->dev;
0081
0082     if (WARN_ON(!ib))
0083         return -EFAULT;
0084
0085     /* Determine the number of processes to map together to HW:
0086      * it can not exceed the number of VMIDs available to the
0087      * scheduler, and it is determined by the smaller of the number
0088      * of processes in the runlist and kfd module parameter
0089      * hws_max_conc_proc.
0090      * Note: the arbitration between the number of VMIDs and
0091      * hws_max_conc_proc has been done in
0092      * kgd2kfd_device_init().
0093      */
0094     concurrent_proc_cnt = min(pm->dqm->processes_count,
0095             kfd->max_proc_per_quantum);
0096
0097     packet = (struct pm4_mes_runlist *)buffer;
0098
0099     memset(buffer, 0, sizeof(struct pm4_mes_runlist));
0100     packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
0101                         sizeof(struct pm4_mes_runlist));
0102
0103     packet->bitfields4.ib_size = ib_size_in_dwords;
0104     packet->bitfields4.chain = chain ? 1 : 0;
0105     packet->bitfields4.offload_polling = 0;
0106     packet->bitfields4.valid = 1;
0107     packet->bitfields4.process_cnt = concurrent_proc_cnt;
0108     packet->ordinal2 = lower_32_bits(ib);
0109     packet->bitfields3.ib_base_hi = upper_32_bits(ib);
0110
0111     return 0;
0112 }
0113
0114 static int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer,
0115                    struct scheduling_resources *res)
0116 {
0117     struct pm4_mes_set_resources *packet;
0118
0119     packet = (struct pm4_mes_set_resources *)buffer;
0120     memset(buffer, 0, sizeof(struct pm4_mes_set_resources));
0121
0122     packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
0123                     sizeof(struct pm4_mes_set_resources));
0124
0125     packet->bitfields2.queue_type =
0126             queue_type__mes_set_resources__hsa_interface_queue_hiq;
0127     packet->bitfields2.vmid_mask = res->vmid_mask;
0128     packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
0129     packet->bitfields7.oac_mask = res->oac_mask;
0130     packet->bitfields8.gds_heap_base = res->gds_heap_base;
0131     packet->bitfields8.gds_heap_size = res->gds_heap_size;
0132
0133     packet->gws_mask_lo = lower_32_bits(res->gws_mask);
0134     packet->gws_mask_hi = upper_32_bits(res->gws_mask);
0135
0136     packet->queue_mask_lo = lower_32_bits(res->queue_mask);
0137     packet->queue_mask_hi = upper_32_bits(res->queue_mask);
0138
0139     return 0;
0140 }
0141
0142 static int pm_map_queues_vi(struct packet_manager *pm, uint32_t *buffer,
0143         struct queue *q, bool is_static)
0144 {
0145     struct pm4_mes_map_queues *packet;
0146     bool use_static = is_static;
0147
0148     packet = (struct pm4_mes_map_queues *)buffer;
0149     memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
0150
0151     packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
0152                     sizeof(struct pm4_mes_map_queues));
0153     packet->bitfields2.num_queues = 1;
0154     packet->bitfields2.queue_sel =
0155         queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
0156
0157     packet->bitfields2.engine_sel =
0158         engine_sel__mes_map_queues__compute_vi;
0159     packet->bitfields2.queue_type =
0160         queue_type__mes_map_queues__normal_compute_vi;
0161
0162     switch (q->properties.type) {
0163     case KFD_QUEUE_TYPE_COMPUTE:
0164         if (use_static)
0165             packet->bitfields2.queue_type =
0166         queue_type__mes_map_queues__normal_latency_static_queue_vi;
0167         break;
0168     case KFD_QUEUE_TYPE_DIQ:
0169         packet->bitfields2.queue_type =
0170             queue_type__mes_map_queues__debug_interface_queue_vi;
0171         break;
0172     case KFD_QUEUE_TYPE_SDMA:
0173     case KFD_QUEUE_TYPE_SDMA_XGMI:
0174         packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
0175                 engine_sel__mes_map_queues__sdma0_vi;
0176         use_static = false; /* no static queues under SDMA */
0177         break;
0178     default:
0179         WARN(1, "queue type %d", q->properties.type);
0180         return -EINVAL;
0181     }
0182     packet->bitfields3.doorbell_offset =
0183             q->properties.doorbell_off;
0184
0185     packet->mqd_addr_lo =
0186             lower_32_bits(q->gart_mqd_addr);
0187
0188     packet->mqd_addr_hi =
0189             upper_32_bits(q->gart_mqd_addr);
0190
0191     packet->wptr_addr_lo =
0192             lower_32_bits((uint64_t)q->properties.write_ptr);
0193
0194     packet->wptr_addr_hi =
0195             upper_32_bits((uint64_t)q->properties.write_ptr);
0196
0197     return 0;
0198 }
0199
0200 static int pm_unmap_queues_vi(struct packet_manager *pm, uint32_t *buffer,
0201             enum kfd_unmap_queues_filter filter,
0202             uint32_t filter_param, bool reset)
0203 {
0204     struct pm4_mes_unmap_queues *packet;
0205
0206     packet = (struct pm4_mes_unmap_queues *)buffer;
0207     memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
0208
0209     packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
0210                     sizeof(struct pm4_mes_unmap_queues));
0211
0212     packet->bitfields2.engine_sel =
0213             engine_sel__mes_unmap_queues__compute;
0214
0215     if (reset)
0216         packet->bitfields2.action =
0217             action__mes_unmap_queues__reset_queues;
0218     else
0219         packet->bitfields2.action =
0220             action__mes_unmap_queues__preempt_queues;
0221
0222     switch (filter) {
0223     case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
0224         packet->bitfields2.queue_sel =
0225             queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
0226         packet->bitfields3a.pasid = filter_param;
0227         break;
0228     case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
0229         packet->bitfields2.queue_sel =
0230             queue_sel__mes_unmap_queues__unmap_all_queues;
0231         break;
0232     case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
0233         /* in this case, we do not preempt static queues */
0234         packet->bitfields2.queue_sel =
0235             queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
0236         break;
0237     default:
0238         WARN(1, "filter %d", filter);
0239         return -EINVAL;
0240     }
0241
0242     return 0;
0243
0244 }
0245
0246 static int pm_query_status_vi(struct packet_manager *pm, uint32_t *buffer,
0247             uint64_t fence_address, uint64_t fence_value)
0248 {
0249     struct pm4_mes_query_status *packet;
0250
0251     packet = (struct pm4_mes_query_status *)buffer;
0252     memset(buffer, 0, sizeof(struct pm4_mes_query_status));
0253
0254     packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
0255                     sizeof(struct pm4_mes_query_status));
0256
0257     packet->bitfields2.context_id = 0;
0258     packet->bitfields2.interrupt_sel =
0259             interrupt_sel__mes_query_status__completion_status;
0260     packet->bitfields2.command =
0261             command__mes_query_status__fence_only_after_write_ack;
0262
0263     packet->addr_hi = upper_32_bits((uint64_t)fence_address);
0264     packet->addr_lo = lower_32_bits((uint64_t)fence_address);
0265     packet->data_hi = upper_32_bits((uint64_t)fence_value);
0266     packet->data_lo = lower_32_bits((uint64_t)fence_value);
0267
0268     return 0;
0269 }
0270
0271 static int pm_release_mem_vi(uint64_t gpu_addr, uint32_t *buffer)
0272 {
0273     struct pm4_mec_release_mem *packet;
0274
0275     packet = (struct pm4_mec_release_mem *)buffer;
0276     memset(buffer, 0, sizeof(*packet));
0277
0278     packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
0279                          sizeof(*packet));
0280
0281     packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
0282     packet->bitfields2.event_index = event_index___release_mem__end_of_pipe;
0283     packet->bitfields2.tcl1_action_ena = 1;
0284     packet->bitfields2.tc_action_ena = 1;
0285     packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
0286     packet->bitfields2.atc = 0;
0287
0288     packet->bitfields3.data_sel = data_sel___release_mem__send_32_bit_low;
0289     packet->bitfields3.int_sel =
0290         int_sel___release_mem__send_interrupt_after_write_confirm;
0291
0292     packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
0293     packet->address_hi = upper_32_bits(gpu_addr);
0294
0295     packet->data_lo = 0;
0296
0297     return 0;
0298 }
0299
0300 const struct packet_manager_funcs kfd_vi_pm_funcs = {
0301     .map_process        = pm_map_process_vi,
0302     .runlist        = pm_runlist_vi,
0303     .set_resources      = pm_set_resources_vi,
0304     .map_queues     = pm_map_queues_vi,
0305     .unmap_queues       = pm_unmap_queues_vi,
0306     .query_status       = pm_query_status_vi,
0307     .release_mem        = pm_release_mem_vi,
0308     .map_process_size   = sizeof(struct pm4_mes_map_process),
0309     .runlist_size       = sizeof(struct pm4_mes_runlist),
0310     .set_resources_size = sizeof(struct pm4_mes_set_resources),
0311     .map_queues_size    = sizeof(struct pm4_mes_map_queues),
0312     .unmap_queues_size  = sizeof(struct pm4_mes_unmap_queues),
0313     .query_status_size  = sizeof(struct pm4_mes_query_status),
0314     .release_mem_size   = sizeof(struct pm4_mec_release_mem)
0315 };