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0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * Copyright 2016-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024 
0025 #include "kfd_kernel_queue.h"
0026 #include "kfd_device_queue_manager.h"
0027 #include "kfd_pm4_headers_ai.h"
0028 #include "kfd_pm4_headers_aldebaran.h"
0029 #include "kfd_pm4_opcodes.h"
0030 #include "gc/gc_10_1_0_sh_mask.h"
0031 
0032 static int pm_map_process_v9(struct packet_manager *pm,
0033         uint32_t *buffer, struct qcm_process_device *qpd)
0034 {
0035     struct pm4_mes_map_process *packet;
0036     uint64_t vm_page_table_base_addr = qpd->page_table_base;
0037 
0038     packet = (struct pm4_mes_map_process *)buffer;
0039     memset(buffer, 0, sizeof(struct pm4_mes_map_process));
0040     packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
0041                     sizeof(struct pm4_mes_map_process));
0042     packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
0043     packet->bitfields2.process_quantum = 10;
0044     packet->bitfields2.pasid = qpd->pqm->process->pasid;
0045     packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
0046     packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
0047     packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
0048     packet->bitfields14.num_oac = qpd->num_oac;
0049     packet->bitfields14.sdma_enable = 1;
0050     packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
0051 
0052     packet->sh_mem_config = qpd->sh_mem_config;
0053     packet->sh_mem_bases = qpd->sh_mem_bases;
0054     if (qpd->tba_addr) {
0055         packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
0056         /* On GFX9, unlike GFX10, bit TRAP_EN of SQ_SHADER_TBA_HI is
0057          * not defined, so setting it won't do any harm.
0058          */
0059         packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)
0060                 | 1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT;
0061 
0062         packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
0063         packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
0064     }
0065 
0066     packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
0067     packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
0068 
0069     packet->vm_context_page_table_base_addr_lo32 =
0070             lower_32_bits(vm_page_table_base_addr);
0071     packet->vm_context_page_table_base_addr_hi32 =
0072             upper_32_bits(vm_page_table_base_addr);
0073 
0074     return 0;
0075 }
0076 
0077 static int pm_map_process_aldebaran(struct packet_manager *pm,
0078         uint32_t *buffer, struct qcm_process_device *qpd)
0079 {
0080     struct pm4_mes_map_process_aldebaran *packet;
0081     uint64_t vm_page_table_base_addr = qpd->page_table_base;
0082 
0083     packet = (struct pm4_mes_map_process_aldebaran *)buffer;
0084     memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran));
0085     packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
0086             sizeof(struct pm4_mes_map_process_aldebaran));
0087     packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
0088     packet->bitfields2.process_quantum = 10;
0089     packet->bitfields2.pasid = qpd->pqm->process->pasid;
0090     packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
0091     packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
0092     packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
0093     packet->bitfields14.num_oac = qpd->num_oac;
0094     packet->bitfields14.sdma_enable = 1;
0095     packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
0096 
0097     packet->sh_mem_config = qpd->sh_mem_config;
0098     packet->sh_mem_bases = qpd->sh_mem_bases;
0099     if (qpd->tba_addr) {
0100         packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
0101         packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
0102         packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
0103     }
0104 
0105     packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
0106     packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
0107 
0108     packet->vm_context_page_table_base_addr_lo32 =
0109             lower_32_bits(vm_page_table_base_addr);
0110     packet->vm_context_page_table_base_addr_hi32 =
0111             upper_32_bits(vm_page_table_base_addr);
0112 
0113     return 0;
0114 }
0115 
0116 static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,
0117             uint64_t ib, size_t ib_size_in_dwords, bool chain)
0118 {
0119     struct pm4_mes_runlist *packet;
0120 
0121     int concurrent_proc_cnt = 0;
0122     struct kfd_dev *kfd = pm->dqm->dev;
0123 
0124     /* Determine the number of processes to map together to HW:
0125      * it can not exceed the number of VMIDs available to the
0126      * scheduler, and it is determined by the smaller of the number
0127      * of processes in the runlist and kfd module parameter
0128      * hws_max_conc_proc.
0129      * Note: the arbitration between the number of VMIDs and
0130      * hws_max_conc_proc has been done in
0131      * kgd2kfd_device_init().
0132      */
0133     concurrent_proc_cnt = min(pm->dqm->processes_count,
0134             kfd->max_proc_per_quantum);
0135 
0136     packet = (struct pm4_mes_runlist *)buffer;
0137 
0138     memset(buffer, 0, sizeof(struct pm4_mes_runlist));
0139     packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
0140                         sizeof(struct pm4_mes_runlist));
0141 
0142     packet->bitfields4.ib_size = ib_size_in_dwords;
0143     packet->bitfields4.chain = chain ? 1 : 0;
0144     packet->bitfields4.offload_polling = 0;
0145     packet->bitfields4.chained_runlist_idle_disable = chain ? 1 : 0;
0146     packet->bitfields4.valid = 1;
0147     packet->bitfields4.process_cnt = concurrent_proc_cnt;
0148     packet->ordinal2 = lower_32_bits(ib);
0149     packet->ib_base_hi = upper_32_bits(ib);
0150 
0151     return 0;
0152 }
0153 
0154 static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer,
0155                 struct scheduling_resources *res)
0156 {
0157     struct pm4_mes_set_resources *packet;
0158 
0159     packet = (struct pm4_mes_set_resources *)buffer;
0160     memset(buffer, 0, sizeof(struct pm4_mes_set_resources));
0161 
0162     packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
0163                     sizeof(struct pm4_mes_set_resources));
0164 
0165     packet->bitfields2.queue_type =
0166             queue_type__mes_set_resources__hsa_interface_queue_hiq;
0167     packet->bitfields2.vmid_mask = res->vmid_mask;
0168     packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
0169     packet->bitfields7.oac_mask = res->oac_mask;
0170     packet->bitfields8.gds_heap_base = res->gds_heap_base;
0171     packet->bitfields8.gds_heap_size = res->gds_heap_size;
0172 
0173     packet->gws_mask_lo = lower_32_bits(res->gws_mask);
0174     packet->gws_mask_hi = upper_32_bits(res->gws_mask);
0175 
0176     packet->queue_mask_lo = lower_32_bits(res->queue_mask);
0177     packet->queue_mask_hi = upper_32_bits(res->queue_mask);
0178 
0179     return 0;
0180 }
0181 
0182 static inline bool pm_use_ext_eng(struct kfd_dev *dev)
0183 {
0184     return dev->adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 2, 0);
0185 }
0186 
0187 static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
0188         struct queue *q, bool is_static)
0189 {
0190     struct pm4_mes_map_queues *packet;
0191     bool use_static = is_static;
0192 
0193     packet = (struct pm4_mes_map_queues *)buffer;
0194     memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
0195 
0196     packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
0197                     sizeof(struct pm4_mes_map_queues));
0198     packet->bitfields2.num_queues = 1;
0199     packet->bitfields2.queue_sel =
0200         queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
0201 
0202     packet->bitfields2.engine_sel =
0203         engine_sel__mes_map_queues__compute_vi;
0204     packet->bitfields2.gws_control_queue = q->gws ? 1 : 0;
0205     packet->bitfields2.extended_engine_sel =
0206         extended_engine_sel__mes_map_queues__legacy_engine_sel;
0207     packet->bitfields2.queue_type =
0208         queue_type__mes_map_queues__normal_compute_vi;
0209 
0210     switch (q->properties.type) {
0211     case KFD_QUEUE_TYPE_COMPUTE:
0212         if (use_static)
0213             packet->bitfields2.queue_type =
0214         queue_type__mes_map_queues__normal_latency_static_queue_vi;
0215         break;
0216     case KFD_QUEUE_TYPE_DIQ:
0217         packet->bitfields2.queue_type =
0218             queue_type__mes_map_queues__debug_interface_queue_vi;
0219         break;
0220     case KFD_QUEUE_TYPE_SDMA:
0221     case KFD_QUEUE_TYPE_SDMA_XGMI:
0222         use_static = false; /* no static queues under SDMA */
0223         if (q->properties.sdma_engine_id < 2 && !pm_use_ext_eng(q->device))
0224             packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
0225                 engine_sel__mes_map_queues__sdma0_vi;
0226         else {
0227             packet->bitfields2.extended_engine_sel =
0228                 extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
0229             packet->bitfields2.engine_sel = q->properties.sdma_engine_id;
0230         }
0231         break;
0232     default:
0233         WARN(1, "queue type %d", q->properties.type);
0234         return -EINVAL;
0235     }
0236     packet->bitfields3.doorbell_offset =
0237             q->properties.doorbell_off;
0238 
0239     packet->mqd_addr_lo =
0240             lower_32_bits(q->gart_mqd_addr);
0241 
0242     packet->mqd_addr_hi =
0243             upper_32_bits(q->gart_mqd_addr);
0244 
0245     packet->wptr_addr_lo =
0246             lower_32_bits((uint64_t)q->properties.write_ptr);
0247 
0248     packet->wptr_addr_hi =
0249             upper_32_bits((uint64_t)q->properties.write_ptr);
0250 
0251     return 0;
0252 }
0253 
0254 static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer,
0255             enum kfd_unmap_queues_filter filter,
0256             uint32_t filter_param, bool reset)
0257 {
0258     struct pm4_mes_unmap_queues *packet;
0259 
0260     packet = (struct pm4_mes_unmap_queues *)buffer;
0261     memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
0262 
0263     packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
0264                     sizeof(struct pm4_mes_unmap_queues));
0265 
0266     packet->bitfields2.extended_engine_sel = pm_use_ext_eng(pm->dqm->dev) ?
0267         extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel :
0268         extended_engine_sel__mes_unmap_queues__legacy_engine_sel;
0269 
0270     packet->bitfields2.engine_sel =
0271         engine_sel__mes_unmap_queues__compute;
0272 
0273     if (reset)
0274         packet->bitfields2.action =
0275             action__mes_unmap_queues__reset_queues;
0276     else
0277         packet->bitfields2.action =
0278             action__mes_unmap_queues__preempt_queues;
0279 
0280     switch (filter) {
0281     case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
0282         packet->bitfields2.queue_sel =
0283             queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
0284         packet->bitfields3a.pasid = filter_param;
0285         break;
0286     case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
0287         packet->bitfields2.queue_sel =
0288             queue_sel__mes_unmap_queues__unmap_all_queues;
0289         break;
0290     case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
0291         /* in this case, we do not preempt static queues */
0292         packet->bitfields2.queue_sel =
0293             queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
0294         break;
0295     default:
0296         WARN(1, "filter %d", filter);
0297         return -EINVAL;
0298     }
0299 
0300     return 0;
0301 
0302 }
0303 
0304 static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,
0305             uint64_t fence_address, uint64_t fence_value)
0306 {
0307     struct pm4_mes_query_status *packet;
0308 
0309     packet = (struct pm4_mes_query_status *)buffer;
0310     memset(buffer, 0, sizeof(struct pm4_mes_query_status));
0311 
0312 
0313     packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
0314                     sizeof(struct pm4_mes_query_status));
0315 
0316     packet->bitfields2.context_id = 0;
0317     packet->bitfields2.interrupt_sel =
0318             interrupt_sel__mes_query_status__completion_status;
0319     packet->bitfields2.command =
0320             command__mes_query_status__fence_only_after_write_ack;
0321 
0322     packet->addr_hi = upper_32_bits((uint64_t)fence_address);
0323     packet->addr_lo = lower_32_bits((uint64_t)fence_address);
0324     packet->data_hi = upper_32_bits((uint64_t)fence_value);
0325     packet->data_lo = lower_32_bits((uint64_t)fence_value);
0326 
0327     return 0;
0328 }
0329 
0330 const struct packet_manager_funcs kfd_v9_pm_funcs = {
0331     .map_process        = pm_map_process_v9,
0332     .runlist        = pm_runlist_v9,
0333     .set_resources      = pm_set_resources_v9,
0334     .map_queues     = pm_map_queues_v9,
0335     .unmap_queues       = pm_unmap_queues_v9,
0336     .query_status       = pm_query_status_v9,
0337     .release_mem        = NULL,
0338     .map_process_size   = sizeof(struct pm4_mes_map_process),
0339     .runlist_size       = sizeof(struct pm4_mes_runlist),
0340     .set_resources_size = sizeof(struct pm4_mes_set_resources),
0341     .map_queues_size    = sizeof(struct pm4_mes_map_queues),
0342     .unmap_queues_size  = sizeof(struct pm4_mes_unmap_queues),
0343     .query_status_size  = sizeof(struct pm4_mes_query_status),
0344     .release_mem_size   = 0,
0345 };
0346 
0347 const struct packet_manager_funcs kfd_aldebaran_pm_funcs = {
0348     .map_process        = pm_map_process_aldebaran,
0349     .runlist        = pm_runlist_v9,
0350     .set_resources      = pm_set_resources_v9,
0351     .map_queues     = pm_map_queues_v9,
0352     .unmap_queues       = pm_unmap_queues_v9,
0353     .query_status       = pm_query_status_v9,
0354     .release_mem        = NULL,
0355     .map_process_size   = sizeof(struct pm4_mes_map_process_aldebaran),
0356     .runlist_size       = sizeof(struct pm4_mes_runlist),
0357     .set_resources_size = sizeof(struct pm4_mes_set_resources),
0358     .map_queues_size    = sizeof(struct pm4_mes_map_queues),
0359     .unmap_queues_size  = sizeof(struct pm4_mes_unmap_queues),
0360     .query_status_size  = sizeof(struct pm4_mes_query_status),
0361     .release_mem_size   = 0,
0362 };
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