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0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * Copyright 2018-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024 
0025 #include <linux/printk.h>
0026 #include <linux/slab.h>
0027 #include <linux/uaccess.h>
0028 #include "kfd_priv.h"
0029 #include "kfd_mqd_manager.h"
0030 #include "v10_structs.h"
0031 #include "gc/gc_10_1_0_offset.h"
0032 #include "gc/gc_10_1_0_sh_mask.h"
0033 #include "amdgpu_amdkfd.h"
0034 
0035 static inline struct v10_compute_mqd *get_mqd(void *mqd)
0036 {
0037     return (struct v10_compute_mqd *)mqd;
0038 }
0039 
0040 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
0041 {
0042     return (struct v10_sdma_mqd *)mqd;
0043 }
0044 
0045 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
0046             struct mqd_update_info *minfo)
0047 {
0048     struct v10_compute_mqd *m;
0049     uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
0050 
0051     if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) ||
0052         !minfo->cu_mask.ptr)
0053         return;
0054 
0055     mqd_symmetrically_map_cu_mask(mm,
0056         minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);
0057 
0058     m = get_mqd(mqd);
0059     m->compute_static_thread_mgmt_se0 = se_mask[0];
0060     m->compute_static_thread_mgmt_se1 = se_mask[1];
0061     m->compute_static_thread_mgmt_se2 = se_mask[2];
0062     m->compute_static_thread_mgmt_se3 = se_mask[3];
0063 
0064     pr_debug("update cu mask to %#x %#x %#x %#x\n",
0065         m->compute_static_thread_mgmt_se0,
0066         m->compute_static_thread_mgmt_se1,
0067         m->compute_static_thread_mgmt_se2,
0068         m->compute_static_thread_mgmt_se3);
0069 }
0070 
0071 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q)
0072 {
0073     m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
0074     m->cp_hqd_queue_priority = q->priority;
0075 }
0076 
0077 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
0078         struct queue_properties *q)
0079 {
0080     struct kfd_mem_obj *mqd_mem_obj;
0081 
0082     if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
0083             &mqd_mem_obj))
0084         return NULL;
0085 
0086     return mqd_mem_obj;
0087 }
0088 
0089 static void init_mqd(struct mqd_manager *mm, void **mqd,
0090             struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
0091             struct queue_properties *q)
0092 {
0093     uint64_t addr;
0094     struct v10_compute_mqd *m;
0095 
0096     m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
0097     addr = mqd_mem_obj->gpu_addr;
0098 
0099     memset(m, 0, sizeof(struct v10_compute_mqd));
0100 
0101     m->header = 0xC0310800;
0102     m->compute_pipelinestat_enable = 1;
0103     m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
0104     m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
0105     m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
0106     m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
0107 
0108     m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
0109             0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
0110 
0111     m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
0112 
0113     m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
0114     m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
0115 
0116     m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
0117             1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
0118             1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
0119 
0120     if (q->format == KFD_QUEUE_FORMAT_AQL) {
0121         m->cp_hqd_aql_control =
0122             1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
0123     }
0124 
0125     if (mm->dev->cwsr_enabled) {
0126         m->cp_hqd_persistent_state |=
0127             (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
0128         m->cp_hqd_ctx_save_base_addr_lo =
0129             lower_32_bits(q->ctx_save_restore_area_address);
0130         m->cp_hqd_ctx_save_base_addr_hi =
0131             upper_32_bits(q->ctx_save_restore_area_address);
0132         m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
0133         m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
0134         m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
0135         m->cp_hqd_wg_state_offset = q->ctl_stack_size;
0136     }
0137 
0138     *mqd = m;
0139     if (gart_addr)
0140         *gart_addr = addr;
0141     mm->update_mqd(mm, m, q, NULL);
0142 }
0143 
0144 static int load_mqd(struct mqd_manager *mm, void *mqd,
0145             uint32_t pipe_id, uint32_t queue_id,
0146             struct queue_properties *p, struct mm_struct *mms)
0147 {
0148     int r = 0;
0149     /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
0150     uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
0151 
0152     r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
0153                       (uint32_t __user *)p->write_ptr,
0154                       wptr_shift, 0, mms);
0155     return r;
0156 }
0157 
0158 static void update_mqd(struct mqd_manager *mm, void *mqd,
0159             struct queue_properties *q,
0160             struct mqd_update_info *minfo)
0161 {
0162     struct v10_compute_mqd *m;
0163 
0164     m = get_mqd(mqd);
0165 
0166     m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
0167     m->cp_hqd_pq_control |=
0168             ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
0169     pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
0170 
0171     m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
0172     m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
0173 
0174     m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
0175     m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
0176     m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
0177     m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
0178 
0179     m->cp_hqd_pq_doorbell_control =
0180         q->doorbell_off <<
0181             CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
0182     pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
0183             m->cp_hqd_pq_doorbell_control);
0184 
0185     m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;
0186 
0187     /*
0188      * HW does not clamp this field correctly. Maximum EOP queue size
0189      * is constrained by per-SE EOP done signal count, which is 8-bit.
0190      * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
0191      * more than (EOP entry count - 1) so a queue size of 0x800 dwords
0192      * is safe, giving a maximum field value of 0xA.
0193      */
0194     m->cp_hqd_eop_control = min(0xA,
0195         ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
0196     m->cp_hqd_eop_base_addr_lo =
0197             lower_32_bits(q->eop_ring_buffer_address >> 8);
0198     m->cp_hqd_eop_base_addr_hi =
0199             upper_32_bits(q->eop_ring_buffer_address >> 8);
0200 
0201     m->cp_hqd_iq_timer = 0;
0202 
0203     m->cp_hqd_vmid = q->vmid;
0204 
0205     if (q->format == KFD_QUEUE_FORMAT_AQL) {
0206         /* GC 10 removed WPP_CLAMP from PQ Control */
0207         m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
0208                 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
0209                 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT;
0210         m->cp_hqd_pq_doorbell_control |=
0211             1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
0212     }
0213     if (mm->dev->cwsr_enabled)
0214         m->cp_hqd_ctx_save_control = 0;
0215 
0216     update_cu_mask(mm, mqd, minfo);
0217     set_priority(m, q);
0218 
0219     q->is_active = QUEUE_IS_ACTIVE(*q);
0220 }
0221 
0222 static uint32_t read_doorbell_id(void *mqd)
0223 {
0224     struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd;
0225 
0226     return m->queue_doorbell_id0;
0227 }
0228 
0229 static int get_wave_state(struct mqd_manager *mm, void *mqd,
0230               void __user *ctl_stack,
0231               u32 *ctl_stack_used_size,
0232               u32 *save_area_used_size)
0233 {
0234     struct v10_compute_mqd *m;
0235 
0236     m = get_mqd(mqd);
0237 
0238     /* Control stack is written backwards, while workgroup context data
0239      * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
0240      * Current position is at m->cp_hqd_cntl_stack_offset and
0241      * m->cp_hqd_wg_state_offset, respectively.
0242      */
0243     *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
0244         m->cp_hqd_cntl_stack_offset;
0245     *save_area_used_size = m->cp_hqd_wg_state_offset -
0246         m->cp_hqd_cntl_stack_size;
0247 
0248     /* Control stack is not copied to user mode for GFXv10 because
0249      * it's part of the context save area that is already
0250      * accessible to user mode
0251      */
0252 
0253     return 0;
0254 }
0255 
0256 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
0257 {
0258     struct v10_compute_mqd *m;
0259 
0260     m = get_mqd(mqd);
0261 
0262     memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd));
0263 }
0264 
0265 static void restore_mqd(struct mqd_manager *mm, void **mqd,
0266             struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
0267             struct queue_properties *qp,
0268             const void *mqd_src,
0269             const void *ctl_stack_src, const u32 ctl_stack_size)
0270 {
0271     uint64_t addr;
0272     struct v10_compute_mqd *m;
0273 
0274     m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
0275     addr = mqd_mem_obj->gpu_addr;
0276 
0277     memcpy(m, mqd_src, sizeof(*m));
0278 
0279     *mqd = m;
0280     if (gart_addr)
0281         *gart_addr = addr;
0282 
0283     m->cp_hqd_pq_doorbell_control =
0284         qp->doorbell_off <<
0285             CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
0286     pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
0287             m->cp_hqd_pq_doorbell_control);
0288 
0289     qp->is_active = 0;
0290 }
0291 
0292 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
0293             struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
0294             struct queue_properties *q)
0295 {
0296     struct v10_compute_mqd *m;
0297 
0298     init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
0299 
0300     m = get_mqd(*mqd);
0301 
0302     m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
0303             1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
0304 }
0305 
0306 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
0307         struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
0308         struct queue_properties *q)
0309 {
0310     struct v10_sdma_mqd *m;
0311 
0312     m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
0313 
0314     memset(m, 0, sizeof(struct v10_sdma_mqd));
0315 
0316     *mqd = m;
0317     if (gart_addr)
0318         *gart_addr = mqd_mem_obj->gpu_addr;
0319 
0320     mm->update_mqd(mm, m, q, NULL);
0321 }
0322 
0323 #define SDMA_RLC_DUMMY_DEFAULT 0xf
0324 
0325 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
0326             struct queue_properties *q,
0327             struct mqd_update_info *minfo)
0328 {
0329     struct v10_sdma_mqd *m;
0330 
0331     m = get_sdma_mqd(mqd);
0332     m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
0333         << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
0334         q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
0335         1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
0336         6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
0337 
0338     m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
0339     m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
0340     m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
0341     m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
0342     m->sdmax_rlcx_doorbell_offset =
0343         q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
0344 
0345     m->sdma_engine_id = q->sdma_engine_id;
0346     m->sdma_queue_id = q->sdma_queue_id;
0347     m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
0348 
0349     q->is_active = QUEUE_IS_ACTIVE(*q);
0350 }
0351 
0352 static void checkpoint_mqd_sdma(struct mqd_manager *mm,
0353                 void *mqd,
0354                 void *mqd_dst,
0355                 void *ctl_stack_dst)
0356 {
0357     struct v10_sdma_mqd *m;
0358 
0359     m = get_sdma_mqd(mqd);
0360 
0361     memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd));
0362 }
0363 
0364 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd,
0365                  struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
0366                  struct queue_properties *qp,
0367                  const void *mqd_src,
0368                  const void *ctl_stack_src,
0369                  const u32 ctl_stack_size)
0370 {
0371     uint64_t addr;
0372     struct v10_sdma_mqd *m;
0373 
0374     m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
0375     addr = mqd_mem_obj->gpu_addr;
0376 
0377     memcpy(m, mqd_src, sizeof(*m));
0378 
0379     m->sdmax_rlcx_doorbell_offset =
0380         qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
0381 
0382     *mqd = m;
0383     if (gart_addr)
0384         *gart_addr = addr;
0385 
0386     qp->is_active = 0;
0387 }
0388 
0389 #if defined(CONFIG_DEBUG_FS)
0390 
0391 static int debugfs_show_mqd(struct seq_file *m, void *data)
0392 {
0393     seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
0394              data, sizeof(struct v10_compute_mqd), false);
0395     return 0;
0396 }
0397 
0398 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
0399 {
0400     seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
0401              data, sizeof(struct v10_sdma_mqd), false);
0402     return 0;
0403 }
0404 
0405 #endif
0406 
0407 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
0408         struct kfd_dev *dev)
0409 {
0410     struct mqd_manager *mqd;
0411 
0412     if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
0413         return NULL;
0414 
0415     mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
0416     if (!mqd)
0417         return NULL;
0418 
0419     mqd->dev = dev;
0420 
0421     switch (type) {
0422     case KFD_MQD_TYPE_CP:
0423         pr_debug("%s@%i\n", __func__, __LINE__);
0424         mqd->allocate_mqd = allocate_mqd;
0425         mqd->init_mqd = init_mqd;
0426         mqd->free_mqd = kfd_free_mqd_cp;
0427         mqd->load_mqd = load_mqd;
0428         mqd->update_mqd = update_mqd;
0429         mqd->destroy_mqd = kfd_destroy_mqd_cp;
0430         mqd->is_occupied = kfd_is_occupied_cp;
0431         mqd->mqd_size = sizeof(struct v10_compute_mqd);
0432         mqd->get_wave_state = get_wave_state;
0433         mqd->checkpoint_mqd = checkpoint_mqd;
0434         mqd->restore_mqd = restore_mqd;
0435 #if defined(CONFIG_DEBUG_FS)
0436         mqd->debugfs_show_mqd = debugfs_show_mqd;
0437 #endif
0438         pr_debug("%s@%i\n", __func__, __LINE__);
0439         break;
0440     case KFD_MQD_TYPE_HIQ:
0441         pr_debug("%s@%i\n", __func__, __LINE__);
0442         mqd->allocate_mqd = allocate_hiq_mqd;
0443         mqd->init_mqd = init_mqd_hiq;
0444         mqd->free_mqd = free_mqd_hiq_sdma;
0445         mqd->load_mqd = kfd_hiq_load_mqd_kiq;
0446         mqd->update_mqd = update_mqd;
0447         mqd->destroy_mqd = kfd_destroy_mqd_cp;
0448         mqd->is_occupied = kfd_is_occupied_cp;
0449         mqd->mqd_size = sizeof(struct v10_compute_mqd);
0450 #if defined(CONFIG_DEBUG_FS)
0451         mqd->debugfs_show_mqd = debugfs_show_mqd;
0452 #endif
0453         mqd->read_doorbell_id = read_doorbell_id;
0454         pr_debug("%s@%i\n", __func__, __LINE__);
0455         break;
0456     case KFD_MQD_TYPE_DIQ:
0457         mqd->allocate_mqd = allocate_mqd;
0458         mqd->init_mqd = init_mqd_hiq;
0459         mqd->free_mqd = kfd_free_mqd_cp;
0460         mqd->load_mqd = load_mqd;
0461         mqd->update_mqd = update_mqd;
0462         mqd->destroy_mqd = kfd_destroy_mqd_cp;
0463         mqd->is_occupied = kfd_is_occupied_cp;
0464         mqd->mqd_size = sizeof(struct v10_compute_mqd);
0465 #if defined(CONFIG_DEBUG_FS)
0466         mqd->debugfs_show_mqd = debugfs_show_mqd;
0467 #endif
0468         break;
0469     case KFD_MQD_TYPE_SDMA:
0470         pr_debug("%s@%i\n", __func__, __LINE__);
0471         mqd->allocate_mqd = allocate_sdma_mqd;
0472         mqd->init_mqd = init_mqd_sdma;
0473         mqd->free_mqd = free_mqd_hiq_sdma;
0474         mqd->load_mqd = kfd_load_mqd_sdma;
0475         mqd->update_mqd = update_mqd_sdma;
0476         mqd->destroy_mqd = kfd_destroy_mqd_sdma;
0477         mqd->is_occupied = kfd_is_occupied_sdma;
0478         mqd->checkpoint_mqd = checkpoint_mqd_sdma;
0479         mqd->restore_mqd = restore_mqd_sdma;
0480         mqd->mqd_size = sizeof(struct v10_sdma_mqd);
0481 #if defined(CONFIG_DEBUG_FS)
0482         mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
0483 #endif
0484         pr_debug("%s@%i\n", __func__, __LINE__);
0485         break;
0486     default:
0487         kfree(mqd);
0488         return NULL;
0489     }
0490 
0491     return mqd;
0492 }
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