amd/amdkfd/kfd_device_queue_manager_v9.c

0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * Copyright 2016-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #include "kfd_device_queue_manager.h"
0026 #include "vega10_enum.h"
0027 #include "gc/gc_9_0_offset.h"
0028 #include "gc/gc_9_0_sh_mask.h"
0029 #include "sdma0/sdma0_4_0_sh_mask.h"
0030
0031 static int update_qpd_v9(struct device_queue_manager *dqm,
0032              struct qcm_process_device *qpd);
0033 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
0034                 struct qcm_process_device *qpd);
0035
0036 void device_queue_manager_init_v9(
0037     struct device_queue_manager_asic_ops *asic_ops)
0038 {
0039     asic_ops->update_qpd = update_qpd_v9;
0040     asic_ops->init_sdma_vm = init_sdma_vm_v9;
0041     asic_ops->mqd_manager_init = mqd_manager_init_v9;
0042 }
0043
0044 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
0045 {
0046     uint32_t shared_base = pdd->lds_base >> 48;
0047     uint32_t private_base = pdd->scratch_base >> 48;
0048
0049     return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
0050         private_base;
0051 }
0052
0053 static int update_qpd_v9(struct device_queue_manager *dqm,
0054              struct qcm_process_device *qpd)
0055 {
0056     struct kfd_process_device *pdd;
0057
0058     pdd = qpd_to_pdd(qpd);
0059
0060     /* check if sh_mem_config register already configured */
0061     if (qpd->sh_mem_config == 0) {
0062         qpd->sh_mem_config =
0063                 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
0064                     SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
0065
0066         if (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 2)) {
0067             /* Aldebaran can safely support different XNACK modes
0068              * per process
0069              */
0070             if (!pdd->process->xnack_enabled)
0071                 qpd->sh_mem_config |=
0072                     1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
0073         } else if (dqm->dev->noretry &&
0074                !dqm->dev->use_iommu_v2) {
0075             qpd->sh_mem_config |=
0076                 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
0077         }
0078
0079         qpd->sh_mem_ape1_limit = 0;
0080         qpd->sh_mem_ape1_base = 0;
0081     }
0082
0083     qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
0084
0085     pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
0086
0087     return 0;
0088 }
0089
0090 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
0091                 struct qcm_process_device *qpd)
0092 {
0093     /* Not needed on SDMAv4 any more */
0094     q->properties.sdma_vm_addr = 0;
0095 }