amd/amdkfd/kfd_device_queue_manager_v11.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "kfd_device_queue_manager.h"
0025 #include "gc/gc_11_0_0_offset.h"
0026 #include "gc/gc_11_0_0_sh_mask.h"
0027 #include "soc21_enum.h"
0028
0029 static int update_qpd_v11(struct device_queue_manager *dqm,
0030              struct qcm_process_device *qpd);
0031 static void init_sdma_vm_v11(struct device_queue_manager *dqm, struct queue *q,
0032                 struct qcm_process_device *qpd);
0033
0034 void device_queue_manager_init_v11(
0035     struct device_queue_manager_asic_ops *asic_ops)
0036 {
0037     asic_ops->update_qpd = update_qpd_v11;
0038     asic_ops->init_sdma_vm = init_sdma_vm_v11;
0039     asic_ops->mqd_manager_init = mqd_manager_init_v11;
0040 }
0041
0042 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
0043 {
0044     uint32_t shared_base = pdd->lds_base >> 48;
0045     uint32_t private_base = pdd->scratch_base >> 48;
0046
0047     return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
0048         private_base;
0049 }
0050
0051 static int update_qpd_v11(struct device_queue_manager *dqm,
0052              struct qcm_process_device *qpd)
0053 {
0054     struct kfd_process_device *pdd;
0055
0056     pdd = qpd_to_pdd(qpd);
0057
0058     /* check if sh_mem_config register already configured */
0059     if (qpd->sh_mem_config == 0) {
0060         qpd->sh_mem_config =
0061             (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
0062                 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
0063             (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
0064
0065         qpd->sh_mem_ape1_limit = 0;
0066         qpd->sh_mem_ape1_base = 0;
0067     }
0068
0069     qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
0070
0071     pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
0072
0073     return 0;
0074 }
0075
0076 static void init_sdma_vm_v11(struct device_queue_manager *dqm, struct queue *q,
0077                 struct qcm_process_device *qpd)
0078 {
0079     /* Not needed on SDMAv4 onwards any more */
0080     q->properties.sdma_vm_addr = 0;
0081 }