amd/amdkfd/kfd_device_queue_manager_v10.c

0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * Copyright 2018-2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #include "kfd_device_queue_manager.h"
0026 #include "navi10_enum.h"
0027 #include "gc/gc_10_1_0_offset.h"
0028 #include "gc/gc_10_1_0_sh_mask.h"
0029
0030 static int update_qpd_v10(struct device_queue_manager *dqm,
0031              struct qcm_process_device *qpd);
0032 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
0033                 struct qcm_process_device *qpd);
0034
0035 void device_queue_manager_init_v10_navi10(
0036     struct device_queue_manager_asic_ops *asic_ops)
0037 {
0038     asic_ops->update_qpd = update_qpd_v10;
0039     asic_ops->init_sdma_vm = init_sdma_vm_v10;
0040     asic_ops->mqd_manager_init = mqd_manager_init_v10;
0041 }
0042
0043 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
0044 {
0045     uint32_t shared_base = pdd->lds_base >> 48;
0046     uint32_t private_base = pdd->scratch_base >> 48;
0047
0048     return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
0049         private_base;
0050 }
0051
0052 static int update_qpd_v10(struct device_queue_manager *dqm,
0053              struct qcm_process_device *qpd)
0054 {
0055     struct kfd_process_device *pdd;
0056
0057     pdd = qpd_to_pdd(qpd);
0058
0059     /* check if sh_mem_config register already configured */
0060     if (qpd->sh_mem_config == 0) {
0061         qpd->sh_mem_config =
0062             (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
0063                 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
0064             (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
0065         qpd->sh_mem_ape1_limit = 0;
0066         qpd->sh_mem_ape1_base = 0;
0067     }
0068
0069     qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
0070
0071     pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
0072
0073     return 0;
0074 }
0075
0076 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
0077                 struct qcm_process_device *qpd)
0078 {
0079     /* Not needed on SDMAv4 onwards any more */
0080     q->properties.sdma_vm_addr = 0;
0081 }