amd/amdkfd/cik_regs.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #ifndef CIK_REGS_H
0024 #define CIK_REGS_H
0025
0026 /* if PTR32, these are the bases for scratch and lds */
0027 #define PRIVATE_BASE(x)                 ((x) << 0) /* scratch */
0028 #define SHARED_BASE(x)                  ((x) << 16) /* LDS */
0029 #define PTR32                       (1 << 0)
0030 #define ALIGNMENT_MODE(x)               ((x) << 2)
0031 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED         3
0032 #define DEFAULT_MTYPE(x)                ((x) << 4)
0033 #define APE1_MTYPE(x)                   ((x) << 7)
0034
0035 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */
0036 #define MTYPE_CACHED_NV                 0
0037 #define MTYPE_CACHED                    1
0038 #define MTYPE_NONCACHED                 3
0039
0040 #define DEFAULT_CP_HQD_PERSISTENT_STATE         (0x33U << 8)
0041 #define PRELOAD_REQ                 (1 << 0)
0042
0043 #define MQD_CONTROL_PRIV_STATE_EN           (1U << 8)
0044
0045 #define DEFAULT_MIN_IB_AVAIL_SIZE           (3U << 20)
0046
0047 #define IB_ATC_EN                   (1U << 23)
0048
0049 #define QUANTUM_EN                  1U
0050 #define QUANTUM_SCALE_1MS               (1U << 4)
0051 #define QUANTUM_DURATION(x)             ((x) << 8)
0052
0053 #define RPTR_BLOCK_SIZE(x)              ((x) << 8)
0054 #define MIN_AVAIL_SIZE(x)               ((x) << 20)
0055 #define DEFAULT_RPTR_BLOCK_SIZE             RPTR_BLOCK_SIZE(5)
0056 #define DEFAULT_MIN_AVAIL_SIZE              MIN_AVAIL_SIZE(3)
0057
0058 #define PQ_ATC_EN                   (1 << 23)
0059 #define NO_UPDATE_RPTR                  (1 << 27)
0060
0061 #define DOORBELL_OFFSET(x)              ((x) << 2)
0062 #define DOORBELL_EN                 (1 << 30)
0063
0064 #define PRIV_STATE                  (1 << 30)
0065 #define KMD_QUEUE                   (1 << 31)
0066
0067 #define AQL_ENABLE                  1
0068
0069 #define GRBM_GFX_INDEX                  0x30800
0070
0071 #endif