amd/amdgpu/vega10_reg_init.c

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "soc15.h"
0025
0026 #include "soc15_common.h"
0027 #include "vega10_ip_offset.h"
0028
0029 int vega10_reg_base_init(struct amdgpu_device *adev)
0030 {
0031     /* HW has more IP blocks,  only initialized the blocke beend by our driver  */
0032     uint32_t i;
0033     for (i = 0 ; i < MAX_INSTANCE ; ++i) {
0034         adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
0035         adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
0036         adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
0037         adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
0038         adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
0039         adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
0040         adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
0041         adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
0042         adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
0043         adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
0044         adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
0045         adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
0046         adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
0047         adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
0048         adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
0049         adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
0050         adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));
0051         adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));
0052         adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
0053         adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
0054     }
0055     return 0;
0056 }
0057
0058 void vega10_doorbell_index_init(struct amdgpu_device *adev)
0059 {
0060     adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
0061     adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
0062     adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
0063     adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
0064     adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
0065     adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
0066     adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
0067     adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
0068     adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
0069     adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL64_USERQUEUE_START;
0070     adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
0071     adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
0072     adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL64_sDMA_ENGINE0;
0073     adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL64_sDMA_ENGINE1;
0074     adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
0075     adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_DOORBELL64_UVD_RING0_1;
0076     adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_DOORBELL64_UVD_RING2_3;
0077     adev->doorbell_index.uvd_vce.uvd_ring4_5 = AMDGPU_DOORBELL64_UVD_RING4_5;
0078     adev->doorbell_index.uvd_vce.uvd_ring6_7 = AMDGPU_DOORBELL64_UVD_RING6_7;
0079     adev->doorbell_index.uvd_vce.vce_ring0_1 = AMDGPU_DOORBELL64_VCE_RING0_1;
0080     adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
0081     adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
0082     adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
0083     adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1;
0084     adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3;
0085     adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5;
0086     adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7;
0087
0088     adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP;
0089     adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
0090
0091     /* In unit of dword doorbell */
0092     adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
0093     adev->doorbell_index.sdma_doorbell_range = 4;
0094 }
0095