amd/amdgpu/vcn_v2_0.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __VCN_V2_0_H__
0025 #define __VCN_V2_0_H__
0026
0027 extern void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
0028 extern void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
0029 extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
0030 extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0031                 unsigned flags);
0032 extern void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
0033                 struct amdgpu_ib *ib, uint32_t flags);
0034 extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
0035                 uint32_t val, uint32_t mask);
0036 extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
0037                 unsigned vmid, uint64_t pd_addr);
0038 extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
0039                 uint32_t reg, uint32_t val);
0040 extern int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring);
0041
0042 extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring);
0043 extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
0044                 u64 seq, unsigned flags);
0045 extern void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
0046                 struct amdgpu_ib *ib, uint32_t flags);
0047 extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
0048                 uint32_t val, uint32_t mask);
0049 extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
0050                 unsigned int vmid, uint64_t pd_addr);
0051 extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
0052
0053 extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block;
0054
0055 #endif /* __VCN_V2_0_H__ */