amd/amdgpu/vcn_sw_ring.h

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __VCN_SW_RING_H__
0025 #define __VCN_SW_RING_H__
0026
0027 #define VCN_SW_RING_EMIT_FRAME_SIZE \
0028         (4 + /* vcn_dec_sw_ring_emit_vm_flush */ \
0029         5 + 5 + /* vcn_dec_sw_ring_emit_fence x2 vm fence */ \
0030         1) /* vcn_dec_sw_ring_insert_end */
0031
0032 void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
0033     u64 seq, uint32_t flags);
0034 void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring);
0035 void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
0036     struct amdgpu_ib *ib, uint32_t flags);
0037 void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
0038     uint32_t val, uint32_t mask);
0039 void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
0040     uint32_t vmid, uint64_t pd_addr);
0041 void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
0042     uint32_t val);
0043
0044 #endif /* __VCN_SW_RING_H__ */