amd/amdgpu/vcn_sw_ring.c

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "amdgpu.h"
0025 #include "vcn_sw_ring.h"
0026
0027 void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
0028     u64 seq, uint32_t flags)
0029 {
0030     WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
0031
0032     amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
0033     amdgpu_ring_write(ring, addr);
0034     amdgpu_ring_write(ring, upper_32_bits(addr));
0035     amdgpu_ring_write(ring, seq);
0036     amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
0037 }
0038
0039 void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
0040 {
0041     amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
0042 }
0043
0044 void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
0045     struct amdgpu_ib *ib, uint32_t flags)
0046 {
0047     uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
0048
0049     amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
0050     amdgpu_ring_write(ring, vmid);
0051     amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
0052     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
0053     amdgpu_ring_write(ring, ib->length_dw);
0054 }
0055
0056 void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
0057     uint32_t val, uint32_t mask)
0058 {
0059     amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
0060     amdgpu_ring_write(ring, reg << 2);
0061     amdgpu_ring_write(ring, mask);
0062     amdgpu_ring_write(ring, val);
0063 }
0064
0065 void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
0066     uint32_t vmid, uint64_t pd_addr)
0067 {
0068     struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
0069     uint32_t data0, data1, mask;
0070
0071     pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
0072
0073     /* wait for register write */
0074     data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
0075     data1 = lower_32_bits(pd_addr);
0076     mask = 0xffffffff;
0077     vcn_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
0078 }
0079
0080 void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
0081     uint32_t val)
0082 {
0083     amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
0084     amdgpu_ring_write(ring, reg << 2);
0085     amdgpu_ring_write(ring, val);
0086 }