amd/amdgpu/umc_v8_10.h

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __UMC_V8_10_H__
0024 #define __UMC_V8_10_H__
0025
0026 #include "soc15_common.h"
0027 #include "amdgpu.h"
0028
0029 /* number of umc channel instance with memory map register access */
0030 #define UMC_V8_10_CHANNEL_INSTANCE_NUM      2
0031 /* number of umc instance with memory map register access */
0032 #define UMC_V8_10_UMC_INSTANCE_NUM      2
0033
0034 /* Total channel instances for all umc nodes */
0035 #define UMC_V8_10_TOTAL_CHANNEL_NUM(adev) \
0036     (UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * (adev)->umc.node_inst_num)
0037
0038 /* UMC regiser per channel offset */
0039 #define UMC_V8_10_PER_CHANNEL_OFFSET    0x400
0040
0041 /* EccErrCnt max value */
0042 #define UMC_V8_10_CE_CNT_MAX        0xffff
0043 /* umc ce interrupt threshold */
0044 #define UUMC_V8_10_CE_INT_THRESHOLD 0xffff
0045 /* umc ce count initial value */
0046 #define UMC_V8_10_CE_CNT_INIT   (UMC_V8_10_CE_CNT_MAX - UUMC_V8_10_CE_INT_THRESHOLD)
0047
0048 #define UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM    4
0049
0050 /* The C5 bit in NA  address */
0051 #define UMC_V8_10_NA_C5_BIT 14
0052
0053 /* Map to swizzle mode address */
0054 #define SWIZZLE_MODE_TMP_ADDR(na, ch_num, ch_idx) \
0055         ((((na) >> 10) * (ch_num) + (ch_idx)) << 10)
0056 #define SWIZZLE_MODE_ADDR_HI(addr, col_bit)  \
0057         (((addr) >> ((col_bit) + 2)) << ((col_bit) + 2))
0058 #define SWIZZLE_MODE_ADDR_MID(na, col_bit) ((((na) >> 8) & 0x3) << (col_bit))
0059 #define SWIZZLE_MODE_ADDR_LOW(addr, col_bit) \
0060         ((((addr) >> 10) & ((0x1ULL << (col_bit - 8)) - 1)) << 8)
0061 #define SWIZZLE_MODE_ADDR_LSB(na) ((na) & 0xFF)
0062
0063 extern struct amdgpu_umc_ras umc_v8_10_ras;
0064 extern const uint32_t
0065     umc_v8_10_channel_idx_tbl[]
0066                 [UMC_V8_10_UMC_INSTANCE_NUM]
0067                 [UMC_V8_10_CHANNEL_INSTANCE_NUM];
0068
0069 #endif
0070