amd/amdgpu/umc_v6_7.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __UMC_V6_7_H__
0024 #define __UMC_V6_7_H__
0025
0026 #include "soc15_common.h"
0027 #include "amdgpu.h"
0028
0029 /* EccErrCnt max value */
0030 #define UMC_V6_7_CE_CNT_MAX     0xffff
0031 /* umc ce interrupt threshold */
0032 #define UMC_V6_7_CE_INT_THRESHOLD   0xffff
0033 /* umc ce count initial value */
0034 #define UMC_V6_7_CE_CNT_INIT    (UMC_V6_7_CE_CNT_MAX - UMC_V6_7_CE_INT_THRESHOLD)
0035
0036 #define UMC_V6_7_INST_DIST  0x40000
0037
0038 /* number of umc channel instance with memory map register access */
0039 #define UMC_V6_7_UMC_INSTANCE_NUM       4
0040 /* number of umc instance with memory map register access */
0041 #define UMC_V6_7_CHANNEL_INSTANCE_NUM       8
0042 /* total channel instances in one umc block */
0043 #define UMC_V6_7_TOTAL_CHANNEL_NUM  (UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
0044 /* one piece of normalizing address is mapped to 8 pieces of physical address */
0045 #define UMC_V6_7_NA_MAP_PA_NUM  8
0046 /* R14 bit shift should be considered, double the number */
0047 #define UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL   (UMC_V6_7_NA_MAP_PA_NUM * 2)
0048 /* The CH4 bit in SOC physical address */
0049 #define UMC_V6_7_PA_CH4_BIT 12
0050 /* The C2 bit in SOC physical address */
0051 #define UMC_V6_7_PA_C2_BIT  17
0052 /* The R14 bit in SOC physical address */
0053 #define UMC_V6_7_PA_R14_BIT 34
0054 /* UMC regiser per channel offset */
0055 #define UMC_V6_7_PER_CHANNEL_OFFSET     0x400
0056
0057 /* XOR bit 20, 25, 34 of PA into CH4 bit (bit 12 of PA),
0058  * hash bit is only effective when related setting is enabled
0059  */
0060 #define CHANNEL_HASH(channel_idx, pa) (((channel_idx) >> 4) ^ \
0061             (((pa)  >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
0062             (((pa)  >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
0063             (((pa)  >> 34) & 0x1ULL & adev->df.hash_status.hash_1g))
0064 #define SET_CHANNEL_HASH(channel_idx, pa) do { \
0065         (pa) &= ~(0x1ULL << UMC_V6_7_PA_CH4_BIT); \
0066         (pa) |= (CHANNEL_HASH(channel_idx, pa) << UMC_V6_7_PA_CH4_BIT); \
0067     } while (0)
0068
0069 extern struct amdgpu_umc_ras umc_v6_7_ras;
0070 extern const uint32_t
0071     umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
0072 extern const uint32_t
0073     umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
0074
0075 #endif