amd/amdgpu/umc_v6_1.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __UMC_V6_1_H__
0024 #define __UMC_V6_1_H__
0025
0026 #include "soc15_common.h"
0027 #include "amdgpu.h"
0028
0029 /* HBM  Memory Channel Width */
0030 #define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH   128
0031 /* number of umc channel instance with memory map register access */
0032 #define UMC_V6_1_CHANNEL_INSTANCE_NUM       4
0033 /* number of umc instance with memory map register access */
0034 #define UMC_V6_1_UMC_INSTANCE_NUM       8
0035 /* total channel instances in one umc block */
0036 #define UMC_V6_1_TOTAL_CHANNEL_NUM  (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
0037 /* UMC regiser per channel offset */
0038 #define UMC_V6_1_PER_CHANNEL_OFFSET_VG20    0x800
0039 #define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT    0x400
0040
0041 /* EccErrCnt max value */
0042 #define UMC_V6_1_CE_CNT_MAX     0xffff
0043 /* umc ce interrupt threshold */
0044 #define UMC_V6_1_CE_INT_THRESHOLD   0xffff
0045 /* umc ce count initial value */
0046 #define UMC_V6_1_CE_CNT_INIT    (UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
0047
0048 extern struct amdgpu_umc_ras umc_v6_1_ras;
0049 extern const uint32_t
0050     umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
0051
0052 #endif