amd/amdgpu/tonga_ih.c

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include <linux/pci.h>
0025
0026 #include "amdgpu.h"
0027 #include "amdgpu_ih.h"
0028 #include "vid.h"
0029
0030 #include "oss/oss_3_0_d.h"
0031 #include "oss/oss_3_0_sh_mask.h"
0032
0033 #include "bif/bif_5_1_d.h"
0034 #include "bif/bif_5_1_sh_mask.h"
0035
0036 /*
0037  * Interrupts
0038  * Starting with r6xx, interrupts are handled via a ring buffer.
0039  * Ring buffers are areas of GPU accessible memory that the GPU
0040  * writes interrupt vectors into and the host reads vectors out of.
0041  * There is a rptr (read pointer) that determines where the
0042  * host is currently reading, and a wptr (write pointer)
0043  * which determines where the GPU has written.  When the
0044  * pointers are equal, the ring is idle.  When the GPU
0045  * writes vectors to the ring buffer, it increments the
0046  * wptr.  When there is an interrupt, the host then starts
0047  * fetching commands and processing them until the pointers are
0048  * equal again at which point it updates the rptr.
0049  */
0050
0051 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
0052
0053 /**
0054  * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
0055  *
0056  * @adev: amdgpu_device pointer
0057  *
0058  * Enable the interrupt ring buffer (VI).
0059  */
0060 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
0061 {
0062     u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
0063
0064     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
0065     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
0066     WREG32(mmIH_RB_CNTL, ih_rb_cntl);
0067     adev->irq.ih.enabled = true;
0068 }
0069
0070 /**
0071  * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
0072  *
0073  * @adev: amdgpu_device pointer
0074  *
0075  * Disable the interrupt ring buffer (VI).
0076  */
0077 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
0078 {
0079     u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
0080
0081     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
0082     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
0083     WREG32(mmIH_RB_CNTL, ih_rb_cntl);
0084     /* set rptr, wptr to 0 */
0085     WREG32(mmIH_RB_RPTR, 0);
0086     WREG32(mmIH_RB_WPTR, 0);
0087     adev->irq.ih.enabled = false;
0088     adev->irq.ih.rptr = 0;
0089 }
0090
0091 /**
0092  * tonga_ih_irq_init - init and enable the interrupt ring
0093  *
0094  * @adev: amdgpu_device pointer
0095  *
0096  * Allocate a ring buffer for the interrupt controller,
0097  * enable the RLC, disable interrupts, enable the IH
0098  * ring buffer and enable it (VI).
0099  * Called at device load and reume.
0100  * Returns 0 for success, errors for failure.
0101  */
0102 static int tonga_ih_irq_init(struct amdgpu_device *adev)
0103 {
0104     u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
0105     struct amdgpu_ih_ring *ih = &adev->irq.ih;
0106     int rb_bufsz;
0107
0108     /* disable irqs */
0109     tonga_ih_disable_interrupts(adev);
0110
0111     /* setup interrupt control */
0112     WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
0113     interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
0114     /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
0115      * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
0116      */
0117     interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
0118     /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
0119     interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
0120     WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
0121
0122     /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
0123     WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
0124
0125     rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
0126     ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
0127     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
0128     /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
0129     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
0130     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
0131
0132     if (adev->irq.msi_enabled)
0133         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
0134
0135     WREG32(mmIH_RB_CNTL, ih_rb_cntl);
0136
0137     /* set the writeback address whether it's enabled or not */
0138     WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
0139     WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
0140
0141     /* set rptr, wptr to 0 */
0142     WREG32(mmIH_RB_RPTR, 0);
0143     WREG32(mmIH_RB_WPTR, 0);
0144
0145     ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
0146     if (adev->irq.ih.use_doorbell) {
0147         ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
0148                          OFFSET, adev->irq.ih.doorbell_index);
0149         ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
0150                          ENABLE, 1);
0151     } else {
0152         ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
0153                          ENABLE, 0);
0154     }
0155     WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
0156
0157     pci_set_master(adev->pdev);
0158
0159     /* enable interrupts */
0160     tonga_ih_enable_interrupts(adev);
0161
0162     return 0;
0163 }
0164
0165 /**
0166  * tonga_ih_irq_disable - disable interrupts
0167  *
0168  * @adev: amdgpu_device pointer
0169  *
0170  * Disable interrupts on the hw (VI).
0171  */
0172 static void tonga_ih_irq_disable(struct amdgpu_device *adev)
0173 {
0174     tonga_ih_disable_interrupts(adev);
0175
0176     /* Wait and acknowledge irq */
0177     mdelay(1);
0178 }
0179
0180 /**
0181  * tonga_ih_get_wptr - get the IH ring buffer wptr
0182  *
0183  * @adev: amdgpu_device pointer
0184  * @ih: IH ring buffer to fetch wptr
0185  *
0186  * Get the IH ring buffer wptr from either the register
0187  * or the writeback memory buffer (VI).  Also check for
0188  * ring buffer overflow and deal with it.
0189  * Used by cz_irq_process(VI).
0190  * Returns the value of the wptr.
0191  */
0192 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
0193                  struct amdgpu_ih_ring *ih)
0194 {
0195     u32 wptr, tmp;
0196
0197     wptr = le32_to_cpu(*ih->wptr_cpu);
0198
0199     if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
0200         goto out;
0201
0202     /* Double check that the overflow wasn't already cleared. */
0203     wptr = RREG32(mmIH_RB_WPTR);
0204
0205     if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
0206         goto out;
0207
0208     wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
0209
0210     /* When a ring buffer overflow happen start parsing interrupt
0211      * from the last not overwritten vector (wptr + 16). Hopefully
0212      * this should allow us to catchup.
0213      */
0214
0215     dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
0216         wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
0217     ih->rptr = (wptr + 16) & ih->ptr_mask;
0218     tmp = RREG32(mmIH_RB_CNTL);
0219     tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
0220     WREG32(mmIH_RB_CNTL, tmp);
0221
0222 out:
0223     return (wptr & ih->ptr_mask);
0224 }
0225
0226 /**
0227  * tonga_ih_decode_iv - decode an interrupt vector
0228  *
0229  * @adev: amdgpu_device pointer
0230  * @ih: IH ring buffer to decode
0231  * @entry: IV entry to place decoded information into
0232  *
0233  * Decodes the interrupt vector at the current rptr
0234  * position and also advance the position.
0235  */
0236 static void tonga_ih_decode_iv(struct amdgpu_device *adev,
0237                    struct amdgpu_ih_ring *ih,
0238                    struct amdgpu_iv_entry *entry)
0239 {
0240     /* wptr/rptr are in bytes! */
0241     u32 ring_index = ih->rptr >> 2;
0242     uint32_t dw[4];
0243
0244     dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
0245     dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
0246     dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
0247     dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
0248
0249     entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
0250     entry->src_id = dw[0] & 0xff;
0251     entry->src_data[0] = dw[1] & 0xfffffff;
0252     entry->ring_id = dw[2] & 0xff;
0253     entry->vmid = (dw[2] >> 8) & 0xff;
0254     entry->pasid = (dw[2] >> 16) & 0xffff;
0255
0256     /* wptr/rptr are in bytes! */
0257     ih->rptr += 16;
0258 }
0259
0260 /**
0261  * tonga_ih_set_rptr - set the IH ring buffer rptr
0262  *
0263  * @adev: amdgpu_device pointer
0264  * @ih: IH ring buffer to set rptr
0265  *
0266  * Set the IH ring buffer rptr.
0267  */
0268 static void tonga_ih_set_rptr(struct amdgpu_device *adev,
0269                   struct amdgpu_ih_ring *ih)
0270 {
0271     if (ih->use_doorbell) {
0272         /* XXX check if swapping is necessary on BE */
0273         *ih->rptr_cpu = ih->rptr;
0274         WDOORBELL32(ih->doorbell_index, ih->rptr);
0275     } else {
0276         WREG32(mmIH_RB_RPTR, ih->rptr);
0277     }
0278 }
0279
0280 static int tonga_ih_early_init(void *handle)
0281 {
0282     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0283     int ret;
0284
0285     ret = amdgpu_irq_add_domain(adev);
0286     if (ret)
0287         return ret;
0288
0289     tonga_ih_set_interrupt_funcs(adev);
0290
0291     return 0;
0292 }
0293
0294 static int tonga_ih_sw_init(void *handle)
0295 {
0296     int r;
0297     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0298
0299     r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
0300     if (r)
0301         return r;
0302
0303     adev->irq.ih.use_doorbell = true;
0304     adev->irq.ih.doorbell_index = adev->doorbell_index.ih;
0305
0306     r = amdgpu_irq_init(adev);
0307
0308     return r;
0309 }
0310
0311 static int tonga_ih_sw_fini(void *handle)
0312 {
0313     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0314
0315     amdgpu_irq_fini_sw(adev);
0316     amdgpu_irq_remove_domain(adev);
0317
0318     return 0;
0319 }
0320
0321 static int tonga_ih_hw_init(void *handle)
0322 {
0323     int r;
0324     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0325
0326     r = tonga_ih_irq_init(adev);
0327     if (r)
0328         return r;
0329
0330     return 0;
0331 }
0332
0333 static int tonga_ih_hw_fini(void *handle)
0334 {
0335     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0336
0337     tonga_ih_irq_disable(adev);
0338
0339     return 0;
0340 }
0341
0342 static int tonga_ih_suspend(void *handle)
0343 {
0344     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0345
0346     return tonga_ih_hw_fini(adev);
0347 }
0348
0349 static int tonga_ih_resume(void *handle)
0350 {
0351     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0352
0353     return tonga_ih_hw_init(adev);
0354 }
0355
0356 static bool tonga_ih_is_idle(void *handle)
0357 {
0358     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0359     u32 tmp = RREG32(mmSRBM_STATUS);
0360
0361     if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
0362         return false;
0363
0364     return true;
0365 }
0366
0367 static int tonga_ih_wait_for_idle(void *handle)
0368 {
0369     unsigned i;
0370     u32 tmp;
0371     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0372
0373     for (i = 0; i < adev->usec_timeout; i++) {
0374         /* read MC_STATUS */
0375         tmp = RREG32(mmSRBM_STATUS);
0376         if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
0377             return 0;
0378         udelay(1);
0379     }
0380     return -ETIMEDOUT;
0381 }
0382
0383 static bool tonga_ih_check_soft_reset(void *handle)
0384 {
0385     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0386     u32 srbm_soft_reset = 0;
0387     u32 tmp = RREG32(mmSRBM_STATUS);
0388
0389     if (tmp & SRBM_STATUS__IH_BUSY_MASK)
0390         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
0391                         SOFT_RESET_IH, 1);
0392
0393     if (srbm_soft_reset) {
0394         adev->irq.srbm_soft_reset = srbm_soft_reset;
0395         return true;
0396     } else {
0397         adev->irq.srbm_soft_reset = 0;
0398         return false;
0399     }
0400 }
0401
0402 static int tonga_ih_pre_soft_reset(void *handle)
0403 {
0404     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0405
0406     if (!adev->irq.srbm_soft_reset)
0407         return 0;
0408
0409     return tonga_ih_hw_fini(adev);
0410 }
0411
0412 static int tonga_ih_post_soft_reset(void *handle)
0413 {
0414     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0415
0416     if (!adev->irq.srbm_soft_reset)
0417         return 0;
0418
0419     return tonga_ih_hw_init(adev);
0420 }
0421
0422 static int tonga_ih_soft_reset(void *handle)
0423 {
0424     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0425     u32 srbm_soft_reset;
0426
0427     if (!adev->irq.srbm_soft_reset)
0428         return 0;
0429     srbm_soft_reset = adev->irq.srbm_soft_reset;
0430
0431     if (srbm_soft_reset) {
0432         u32 tmp;
0433
0434         tmp = RREG32(mmSRBM_SOFT_RESET);
0435         tmp |= srbm_soft_reset;
0436         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
0437         WREG32(mmSRBM_SOFT_RESET, tmp);
0438         tmp = RREG32(mmSRBM_SOFT_RESET);
0439
0440         udelay(50);
0441
0442         tmp &= ~srbm_soft_reset;
0443         WREG32(mmSRBM_SOFT_RESET, tmp);
0444         tmp = RREG32(mmSRBM_SOFT_RESET);
0445
0446         /* Wait a little for things to settle down */
0447         udelay(50);
0448     }
0449
0450     return 0;
0451 }
0452
0453 static int tonga_ih_set_clockgating_state(void *handle,
0454                       enum amd_clockgating_state state)
0455 {
0456     return 0;
0457 }
0458
0459 static int tonga_ih_set_powergating_state(void *handle,
0460                       enum amd_powergating_state state)
0461 {
0462     return 0;
0463 }
0464
0465 static const struct amd_ip_funcs tonga_ih_ip_funcs = {
0466     .name = "tonga_ih",
0467     .early_init = tonga_ih_early_init,
0468     .late_init = NULL,
0469     .sw_init = tonga_ih_sw_init,
0470     .sw_fini = tonga_ih_sw_fini,
0471     .hw_init = tonga_ih_hw_init,
0472     .hw_fini = tonga_ih_hw_fini,
0473     .suspend = tonga_ih_suspend,
0474     .resume = tonga_ih_resume,
0475     .is_idle = tonga_ih_is_idle,
0476     .wait_for_idle = tonga_ih_wait_for_idle,
0477     .check_soft_reset = tonga_ih_check_soft_reset,
0478     .pre_soft_reset = tonga_ih_pre_soft_reset,
0479     .soft_reset = tonga_ih_soft_reset,
0480     .post_soft_reset = tonga_ih_post_soft_reset,
0481     .set_clockgating_state = tonga_ih_set_clockgating_state,
0482     .set_powergating_state = tonga_ih_set_powergating_state,
0483 };
0484
0485 static const struct amdgpu_ih_funcs tonga_ih_funcs = {
0486     .get_wptr = tonga_ih_get_wptr,
0487     .decode_iv = tonga_ih_decode_iv,
0488     .set_rptr = tonga_ih_set_rptr
0489 };
0490
0491 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
0492 {
0493     adev->irq.ih_funcs = &tonga_ih_funcs;
0494 }
0495
0496 const struct amdgpu_ip_block_version tonga_ih_ip_block =
0497 {
0498     .type = AMD_IP_BLOCK_TYPE_IH,
0499     .major = 3,
0500     .minor = 0,
0501     .rev = 0,
0502     .funcs = &tonga_ih_ip_funcs,
0503 };