amd/amdgpu/ta_ras_if.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _TA_RAS_IF_H
0025 #define _TA_RAS_IF_H
0026
0027 #define RAS_TA_HOST_IF_VER  0
0028
0029 /* Responses have bit 31 set */
0030 #define RSP_ID_MASK (1U << 31)
0031 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
0032
0033 /* RAS related enumerations */
0034 /**********************************************************/
0035 enum ras_command {
0036     TA_RAS_COMMAND__ENABLE_FEATURES = 0,
0037     TA_RAS_COMMAND__DISABLE_FEATURES,
0038     TA_RAS_COMMAND__TRIGGER_ERROR,
0039 };
0040
0041 enum ta_ras_status {
0042     TA_RAS_STATUS__SUCCESS                          = 0x0000,
0043     TA_RAS_STATUS__RESET_NEEDED                     = 0xA001,
0044     TA_RAS_STATUS__ERROR_INVALID_PARAMETER          = 0xA002,
0045     TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE          = 0xA003,
0046     TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD          = 0xA004,
0047     TA_RAS_STATUS__ERROR_INJECTION_FAILED           = 0xA005,
0048     TA_RAS_STATUS__ERROR_ASD_READ_WRITE             = 0xA006,
0049     TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE           = 0xA007,
0050     TA_RAS_STATUS__ERROR_TIMEOUT                    = 0xA008,
0051     TA_RAS_STATUS__ERROR_BLOCK_DISABLED             = 0XA009,
0052     TA_RAS_STATUS__ERROR_GENERIC                    = 0xA00A,
0053     TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT             = 0xA00B,
0054     TA_RAS_STATUS__ERROR_GET_DEV_INFO               = 0xA00C,
0055     TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV            = 0xA00D,
0056     TA_RAS_STATUS__ERROR_NOT_INITIALIZED            = 0xA00E,
0057     TA_RAS_STATUS__ERROR_TEE_INTERNAL               = 0xA00F,
0058     TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION       = 0xA010,
0059     TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS         = 0xA011,
0060     TA_RAS_STATUS__ERROR_RAS_READ_WRITE             = 0xA012,
0061     TA_RAS_STATUS__ERROR_NULL_PTR                   = 0xA013,
0062     TA_RAS_STATUS__ERROR_UNSUPPORTED_IP             = 0xA014,
0063     TA_RAS_STATUS__ERROR_PCS_STATE_QUIET            = 0xA015,
0064     TA_RAS_STATUS__ERROR_PCS_STATE_ERROR            = 0xA016,
0065     TA_RAS_STATUS__ERROR_PCS_STATE_HANG             = 0xA017,
0066     TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN          = 0xA018,
0067     TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ      = 0xA019,
0068     TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED          = 0xA01A
0069 };
0070
0071 enum ta_ras_block {
0072     TA_RAS_BLOCK__UMC = 0,
0073     TA_RAS_BLOCK__SDMA,
0074     TA_RAS_BLOCK__GFX,
0075     TA_RAS_BLOCK__MMHUB,
0076     TA_RAS_BLOCK__ATHUB,
0077     TA_RAS_BLOCK__PCIE_BIF,
0078     TA_RAS_BLOCK__HDP,
0079     TA_RAS_BLOCK__XGMI_WAFL,
0080     TA_RAS_BLOCK__DF,
0081     TA_RAS_BLOCK__SMN,
0082     TA_RAS_BLOCK__SEM,
0083     TA_RAS_BLOCK__MP0,
0084     TA_RAS_BLOCK__MP1,
0085     TA_RAS_BLOCK__FUSE,
0086     TA_RAS_BLOCK__MCA,
0087     TA_NUM_BLOCK_MAX
0088 };
0089
0090 enum ta_ras_mca_block {
0091     TA_RAS_MCA_BLOCK__MP0   = 0,
0092     TA_RAS_MCA_BLOCK__MP1   = 1,
0093     TA_RAS_MCA_BLOCK__MPIO  = 2,
0094     TA_RAS_MCA_BLOCK__IOHC  = 3,
0095     TA_MCA_NUM_BLOCK_MAX
0096 };
0097
0098 enum ta_ras_error_type {
0099     TA_RAS_ERROR__NONE          = 0,
0100     TA_RAS_ERROR__PARITY            = 1,
0101     TA_RAS_ERROR__SINGLE_CORRECTABLE    = 2,
0102     TA_RAS_ERROR__MULTI_UNCORRECTABLE   = 4,
0103     TA_RAS_ERROR__POISON            = 8,
0104 };
0105
0106 /* Input/output structures for RAS commands */
0107 /**********************************************************/
0108
0109 struct ta_ras_enable_features_input {
0110     enum ta_ras_block   block_id;
0111     enum ta_ras_error_type  error_type;
0112 };
0113
0114 struct ta_ras_disable_features_input {
0115     enum ta_ras_block   block_id;
0116     enum ta_ras_error_type  error_type;
0117 };
0118
0119 struct ta_ras_trigger_error_input {
0120     enum ta_ras_block   block_id;       // ras-block. i.e. umc, gfx
0121     enum ta_ras_error_type  inject_error_type;  // type of error. i.e. single_correctable
0122     uint32_t        sub_block_index;    // mem block. i.e. hbm, sram etc.
0123     uint64_t        address;        // explicit address of error
0124     uint64_t        value;          // method if error injection. i.e persistent, coherent etc.
0125 };
0126
0127 struct ta_ras_init_flags {
0128     uint8_t poison_mode_en;
0129     uint8_t dgpu_mode;
0130 };
0131
0132 struct ta_ras_output_flags {
0133     uint8_t ras_init_success_flag;
0134     uint8_t err_inject_switch_disable_flag;
0135     uint8_t reg_access_failure_flag;
0136 };
0137
0138 /* Common input structure for RAS callbacks */
0139 /**********************************************************/
0140 union ta_ras_cmd_input {
0141     struct ta_ras_init_flags        init_flags;
0142     struct ta_ras_enable_features_input enable_features;
0143     struct ta_ras_disable_features_input    disable_features;
0144     struct ta_ras_trigger_error_input   trigger_error;
0145
0146     uint32_t reserve_pad[256];
0147 };
0148
0149 union ta_ras_cmd_output {
0150     struct ta_ras_output_flags flags;
0151
0152     uint32_t reserve_pad[256];
0153 };
0154
0155 /* Shared Memory structures */
0156 /**********************************************************/
0157 struct ta_ras_shared_memory {
0158     uint32_t            cmd_id;
0159     uint32_t            resp_id;
0160     uint32_t                ras_status;
0161     uint32_t            if_version;
0162     union ta_ras_cmd_input      ras_in_message;
0163     union ta_ras_cmd_output     ras_out_message;
0164 };
0165
0166 #endif // TL_RAS_IF_H_