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0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/firmware.h>
0024 #include <linux/slab.h>
0025 #include <linux/module.h>
0026 #include <linux/pci.h>
0027 
0028 #include "amdgpu.h"
0029 #include "amdgpu_atombios.h"
0030 #include "amdgpu_ih.h"
0031 #include "amdgpu_uvd.h"
0032 #include "amdgpu_vce.h"
0033 #include "amdgpu_ucode.h"
0034 #include "amdgpu_psp.h"
0035 #include "amdgpu_smu.h"
0036 #include "atom.h"
0037 #include "amd_pcie.h"
0038 
0039 #include "gc/gc_11_0_0_offset.h"
0040 #include "gc/gc_11_0_0_sh_mask.h"
0041 #include "mp/mp_13_0_0_offset.h"
0042 
0043 #include "soc15.h"
0044 #include "soc15_common.h"
0045 #include "soc21.h"
0046 
0047 static const struct amd_ip_funcs soc21_common_ip_funcs;
0048 
0049 /* SOC21 */
0050 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] =
0051 {
0052     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
0053     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
0054 };
0055 
0056 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode =
0057 {
0058     .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array),
0059     .codec_array = vcn_4_0_0_video_codecs_encode_array,
0060 };
0061 
0062 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array[] =
0063 {
0064     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0065     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
0066     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0067     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
0068     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
0069 };
0070 
0071 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode =
0072 {
0073     .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array),
0074     .codec_array = vcn_4_0_0_video_codecs_decode_array,
0075 };
0076 
0077 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
0078                  const struct amdgpu_video_codecs **codecs)
0079 {
0080     switch (adev->ip_versions[UVD_HWIP][0]) {
0081 
0082     case IP_VERSION(4, 0, 0):
0083     case IP_VERSION(4, 0, 2):
0084         if (encode)
0085             *codecs = &vcn_4_0_0_video_codecs_encode;
0086         else
0087             *codecs = &vcn_4_0_0_video_codecs_decode;
0088         return 0;
0089     default:
0090         return -EINVAL;
0091     }
0092 }
0093 /*
0094  * Indirect registers accessor
0095  */
0096 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg)
0097 {
0098     unsigned long address, data;
0099     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0100     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0101 
0102     return amdgpu_device_indirect_rreg(adev, address, data, reg);
0103 }
0104 
0105 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0106 {
0107     unsigned long address, data;
0108 
0109     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0110     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0111 
0112     amdgpu_device_indirect_wreg(adev, address, data, reg, v);
0113 }
0114 
0115 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
0116 {
0117     unsigned long address, data;
0118     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0119     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0120 
0121     return amdgpu_device_indirect_rreg64(adev, address, data, reg);
0122 }
0123 
0124 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
0125 {
0126     unsigned long address, data;
0127 
0128     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0129     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0130 
0131     amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
0132 }
0133 
0134 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
0135 {
0136     unsigned long flags, address, data;
0137     u32 r;
0138 
0139     address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
0140     data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
0141 
0142     spin_lock_irqsave(&adev->didt_idx_lock, flags);
0143     WREG32(address, (reg));
0144     r = RREG32(data);
0145     spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
0146     return r;
0147 }
0148 
0149 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0150 {
0151     unsigned long flags, address, data;
0152 
0153     address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
0154     data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
0155 
0156     spin_lock_irqsave(&adev->didt_idx_lock, flags);
0157     WREG32(address, (reg));
0158     WREG32(data, (v));
0159     spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
0160 }
0161 
0162 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
0163 {
0164     return adev->nbio.funcs->get_memsize(adev);
0165 }
0166 
0167 static u32 soc21_get_xclk(struct amdgpu_device *adev)
0168 {
0169     return adev->clock.spll.reference_freq;
0170 }
0171 
0172 
0173 void soc21_grbm_select(struct amdgpu_device *adev,
0174              u32 me, u32 pipe, u32 queue, u32 vmid)
0175 {
0176     u32 grbm_gfx_cntl = 0;
0177     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
0178     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
0179     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
0180     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
0181 
0182     WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL), grbm_gfx_cntl);
0183 }
0184 
0185 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state)
0186 {
0187     /* todo */
0188 }
0189 
0190 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
0191 {
0192     /* todo */
0193     return false;
0194 }
0195 
0196 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
0197     { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
0198     { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
0199     { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
0200     { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
0201     { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
0202     { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
0203     { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
0204     { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
0205     { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
0206     { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
0207     { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
0208     { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
0209     { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
0210     { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
0211     { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
0212     { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
0213     { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
0214     { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
0215     { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
0216 };
0217 
0218 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
0219                      u32 sh_num, u32 reg_offset)
0220 {
0221     uint32_t val;
0222 
0223     mutex_lock(&adev->grbm_idx_mutex);
0224     if (se_num != 0xffffffff || sh_num != 0xffffffff)
0225         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
0226 
0227     val = RREG32(reg_offset);
0228 
0229     if (se_num != 0xffffffff || sh_num != 0xffffffff)
0230         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
0231     mutex_unlock(&adev->grbm_idx_mutex);
0232     return val;
0233 }
0234 
0235 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
0236                       bool indexed, u32 se_num,
0237                       u32 sh_num, u32 reg_offset)
0238 {
0239     if (indexed) {
0240         return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
0241     } else {
0242         if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
0243             return adev->gfx.config.gb_addr_config;
0244         return RREG32(reg_offset);
0245     }
0246 }
0247 
0248 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
0249                 u32 sh_num, u32 reg_offset, u32 *value)
0250 {
0251     uint32_t i;
0252     struct soc15_allowed_register_entry  *en;
0253 
0254     *value = 0;
0255     for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
0256         en = &soc21_allowed_read_registers[i];
0257         if (adev->reg_offset[en->hwip][en->inst] &&
0258             reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
0259                    + en->reg_offset))
0260             continue;
0261 
0262         *value = soc21_get_register_value(adev,
0263                            soc21_allowed_read_registers[i].grbm_indexed,
0264                            se_num, sh_num, reg_offset);
0265         return 0;
0266     }
0267     return -EINVAL;
0268 }
0269 
0270 #if 0
0271 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
0272 {
0273     u32 i;
0274     int ret = 0;
0275 
0276     amdgpu_atombios_scratch_regs_engine_hung(adev, true);
0277 
0278     /* disable BM */
0279     pci_clear_master(adev->pdev);
0280 
0281     amdgpu_device_cache_pci_state(adev->pdev);
0282 
0283     if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
0284         dev_info(adev->dev, "GPU smu mode1 reset\n");
0285         ret = amdgpu_dpm_mode1_reset(adev);
0286     } else {
0287         dev_info(adev->dev, "GPU psp mode1 reset\n");
0288         ret = psp_gpu_reset(adev);
0289     }
0290 
0291     if (ret)
0292         dev_err(adev->dev, "GPU mode1 reset failed\n");
0293     amdgpu_device_load_pci_state(adev->pdev);
0294 
0295     /* wait for asic to come out of reset */
0296     for (i = 0; i < adev->usec_timeout; i++) {
0297         u32 memsize = adev->nbio.funcs->get_memsize(adev);
0298 
0299         if (memsize != 0xffffffff)
0300             break;
0301         udelay(1);
0302     }
0303 
0304     amdgpu_atombios_scratch_regs_engine_hung(adev, false);
0305 
0306     return ret;
0307 }
0308 #endif
0309 
0310 static enum amd_reset_method
0311 soc21_asic_reset_method(struct amdgpu_device *adev)
0312 {
0313     if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
0314         amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
0315         amdgpu_reset_method == AMD_RESET_METHOD_BACO)
0316         return amdgpu_reset_method;
0317 
0318     if (amdgpu_reset_method != -1)
0319         dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
0320                   amdgpu_reset_method);
0321 
0322     switch (adev->ip_versions[MP1_HWIP][0]) {
0323     case IP_VERSION(13, 0, 0):
0324     case IP_VERSION(13, 0, 7):
0325         return AMD_RESET_METHOD_MODE1;
0326     case IP_VERSION(13, 0, 4):
0327         return AMD_RESET_METHOD_MODE2;
0328     default:
0329         if (amdgpu_dpm_is_baco_supported(adev))
0330             return AMD_RESET_METHOD_BACO;
0331         else
0332             return AMD_RESET_METHOD_MODE1;
0333     }
0334 }
0335 
0336 static int soc21_asic_reset(struct amdgpu_device *adev)
0337 {
0338     int ret = 0;
0339 
0340     switch (soc21_asic_reset_method(adev)) {
0341     case AMD_RESET_METHOD_PCI:
0342         dev_info(adev->dev, "PCI reset\n");
0343         ret = amdgpu_device_pci_reset(adev);
0344         break;
0345     case AMD_RESET_METHOD_BACO:
0346         dev_info(adev->dev, "BACO reset\n");
0347         ret = amdgpu_dpm_baco_reset(adev);
0348         break;
0349     case AMD_RESET_METHOD_MODE2:
0350         dev_info(adev->dev, "MODE2 reset\n");
0351         ret = amdgpu_dpm_mode2_reset(adev);
0352         break;
0353     default:
0354         dev_info(adev->dev, "MODE1 reset\n");
0355         ret = amdgpu_device_mode1_reset(adev);
0356         break;
0357     }
0358 
0359     return ret;
0360 }
0361 
0362 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
0363 {
0364     /* todo */
0365     return 0;
0366 }
0367 
0368 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
0369 {
0370     /* todo */
0371     return 0;
0372 }
0373 
0374 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
0375 {
0376     if (pci_is_root_bus(adev->pdev->bus))
0377         return;
0378 
0379     if (amdgpu_pcie_gen2 == 0)
0380         return;
0381 
0382     if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
0383                     CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
0384         return;
0385 
0386     /* todo */
0387 }
0388 
0389 static void soc21_program_aspm(struct amdgpu_device *adev)
0390 {
0391     if (!amdgpu_device_should_use_aspm(adev))
0392         return;
0393 
0394     if (!(adev->flags & AMD_IS_APU) &&
0395         (adev->nbio.funcs->program_aspm))
0396         adev->nbio.funcs->program_aspm(adev);
0397 }
0398 
0399 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,
0400                     bool enable)
0401 {
0402     adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
0403     adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
0404 }
0405 
0406 const struct amdgpu_ip_block_version soc21_common_ip_block =
0407 {
0408     .type = AMD_IP_BLOCK_TYPE_COMMON,
0409     .major = 1,
0410     .minor = 0,
0411     .rev = 0,
0412     .funcs = &soc21_common_ip_funcs,
0413 };
0414 
0415 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev)
0416 {
0417     return adev->nbio.funcs->get_rev_id(adev);
0418 }
0419 
0420 static bool soc21_need_full_reset(struct amdgpu_device *adev)
0421 {
0422     switch (adev->ip_versions[GC_HWIP][0]) {
0423     case IP_VERSION(11, 0, 0):
0424         return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
0425     case IP_VERSION(11, 0, 2):
0426         return false;
0427     default:
0428         return true;
0429     }
0430 }
0431 
0432 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
0433 {
0434     u32 sol_reg;
0435 
0436     if (adev->flags & AMD_IS_APU)
0437         return false;
0438 
0439     /* Check sOS sign of life register to confirm sys driver and sOS
0440      * are already been loaded.
0441      */
0442     sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
0443     if (sol_reg)
0444         return true;
0445 
0446     return false;
0447 }
0448 
0449 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev)
0450 {
0451 
0452     /* TODO
0453      * dummy implement for pcie_replay_count sysfs interface
0454      * */
0455 
0456     return 0;
0457 }
0458 
0459 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
0460 {
0461     adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
0462     adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
0463     adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
0464     adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
0465     adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
0466     adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
0467     adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
0468     adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
0469     adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
0470     adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
0471     adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
0472     adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
0473     adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
0474     adev->doorbell_index.gfx_userqueue_start =
0475         AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
0476     adev->doorbell_index.gfx_userqueue_end =
0477         AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
0478     adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
0479     adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
0480     adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
0481     adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
0482     adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
0483     adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
0484     adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
0485     adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
0486     adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
0487     adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
0488     adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
0489 
0490     adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
0491     adev->doorbell_index.sdma_doorbell_range = 20;
0492 }
0493 
0494 static void soc21_pre_asic_init(struct amdgpu_device *adev)
0495 {
0496 }
0497 
0498 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
0499                       bool enter)
0500 {
0501     if (enter)
0502         amdgpu_gfx_rlc_enter_safe_mode(adev);
0503     else
0504         amdgpu_gfx_rlc_exit_safe_mode(adev);
0505 
0506     if (adev->gfx.funcs->update_perfmon_mgcg)
0507         adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
0508 
0509     return 0;
0510 }
0511 
0512 static const struct amdgpu_asic_funcs soc21_asic_funcs =
0513 {
0514     .read_disabled_bios = &soc21_read_disabled_bios,
0515     .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
0516     .read_register = &soc21_read_register,
0517     .reset = &soc21_asic_reset,
0518     .reset_method = &soc21_asic_reset_method,
0519     .set_vga_state = &soc21_vga_set_state,
0520     .get_xclk = &soc21_get_xclk,
0521     .set_uvd_clocks = &soc21_set_uvd_clocks,
0522     .set_vce_clocks = &soc21_set_vce_clocks,
0523     .get_config_memsize = &soc21_get_config_memsize,
0524     .init_doorbell_index = &soc21_init_doorbell_index,
0525     .need_full_reset = &soc21_need_full_reset,
0526     .need_reset_on_init = &soc21_need_reset_on_init,
0527     .get_pcie_replay_count = &soc21_get_pcie_replay_count,
0528     .supports_baco = &amdgpu_dpm_is_baco_supported,
0529     .pre_asic_init = &soc21_pre_asic_init,
0530     .query_video_codecs = &soc21_query_video_codecs,
0531     .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
0532 };
0533 
0534 static int soc21_common_early_init(void *handle)
0535 {
0536 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
0537     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0538 
0539     adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
0540     adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
0541     adev->smc_rreg = NULL;
0542     adev->smc_wreg = NULL;
0543     adev->pcie_rreg = &soc21_pcie_rreg;
0544     adev->pcie_wreg = &soc21_pcie_wreg;
0545     adev->pcie_rreg64 = &soc21_pcie_rreg64;
0546     adev->pcie_wreg64 = &soc21_pcie_wreg64;
0547     adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
0548     adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
0549 
0550     /* TODO: will add them during VCN v2 implementation */
0551     adev->uvd_ctx_rreg = NULL;
0552     adev->uvd_ctx_wreg = NULL;
0553 
0554     adev->didt_rreg = &soc21_didt_rreg;
0555     adev->didt_wreg = &soc21_didt_wreg;
0556 
0557     adev->asic_funcs = &soc21_asic_funcs;
0558 
0559     adev->rev_id = soc21_get_rev_id(adev);
0560     adev->external_rev_id = 0xff;
0561     switch (adev->ip_versions[GC_HWIP][0]) {
0562     case IP_VERSION(11, 0, 0):
0563         adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
0564             AMD_CG_SUPPORT_GFX_CGLS |
0565 #if 0
0566             AMD_CG_SUPPORT_GFX_3D_CGCG |
0567             AMD_CG_SUPPORT_GFX_3D_CGLS |
0568 #endif
0569             AMD_CG_SUPPORT_GFX_MGCG |
0570             AMD_CG_SUPPORT_REPEATER_FGCG |
0571             AMD_CG_SUPPORT_GFX_FGCG |
0572             AMD_CG_SUPPORT_GFX_PERF_CLK |
0573             AMD_CG_SUPPORT_VCN_MGCG |
0574             AMD_CG_SUPPORT_JPEG_MGCG |
0575             AMD_CG_SUPPORT_ATHUB_MGCG |
0576             AMD_CG_SUPPORT_ATHUB_LS |
0577             AMD_CG_SUPPORT_MC_MGCG |
0578             AMD_CG_SUPPORT_MC_LS |
0579             AMD_CG_SUPPORT_IH_CG |
0580             AMD_CG_SUPPORT_HDP_SD;
0581         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0582             AMD_PG_SUPPORT_VCN_DPG |
0583             AMD_PG_SUPPORT_JPEG |
0584             AMD_PG_SUPPORT_ATHUB |
0585             AMD_PG_SUPPORT_MMHUB;
0586         adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
0587         break;
0588     case IP_VERSION(11, 0, 2):
0589         adev->cg_flags =
0590             AMD_CG_SUPPORT_GFX_CGCG |
0591             AMD_CG_SUPPORT_GFX_CGLS |
0592             AMD_CG_SUPPORT_REPEATER_FGCG |
0593             AMD_CG_SUPPORT_VCN_MGCG |
0594             AMD_CG_SUPPORT_JPEG_MGCG |
0595             AMD_CG_SUPPORT_ATHUB_MGCG |
0596             AMD_CG_SUPPORT_ATHUB_LS |
0597             AMD_CG_SUPPORT_IH_CG |
0598             AMD_CG_SUPPORT_HDP_SD;
0599         adev->pg_flags =
0600             AMD_PG_SUPPORT_VCN |
0601             AMD_PG_SUPPORT_VCN_DPG |
0602             AMD_PG_SUPPORT_JPEG |
0603             AMD_PG_SUPPORT_ATHUB |
0604             AMD_PG_SUPPORT_MMHUB;
0605         adev->external_rev_id = adev->rev_id + 0x10;
0606         break;
0607     case IP_VERSION(11, 0, 1):
0608         adev->cg_flags =
0609             AMD_CG_SUPPORT_GFX_CGCG |
0610             AMD_CG_SUPPORT_GFX_CGLS |
0611             AMD_CG_SUPPORT_GFX_MGCG |
0612             AMD_CG_SUPPORT_GFX_FGCG |
0613             AMD_CG_SUPPORT_REPEATER_FGCG |
0614             AMD_CG_SUPPORT_GFX_PERF_CLK |
0615             AMD_CG_SUPPORT_MC_MGCG |
0616             AMD_CG_SUPPORT_MC_LS |
0617             AMD_CG_SUPPORT_HDP_MGCG |
0618             AMD_CG_SUPPORT_HDP_LS |
0619             AMD_CG_SUPPORT_ATHUB_MGCG |
0620             AMD_CG_SUPPORT_ATHUB_LS |
0621             AMD_CG_SUPPORT_IH_CG |
0622             AMD_CG_SUPPORT_BIF_MGCG |
0623             AMD_CG_SUPPORT_BIF_LS |
0624             AMD_CG_SUPPORT_VCN_MGCG |
0625             AMD_CG_SUPPORT_JPEG_MGCG;
0626         adev->pg_flags =
0627             AMD_PG_SUPPORT_GFX_PG |
0628             AMD_PG_SUPPORT_VCN_DPG |
0629             AMD_PG_SUPPORT_JPEG;
0630         adev->external_rev_id = adev->rev_id + 0x1;
0631         break;
0632     default:
0633         /* FIXME: not supported yet */
0634         return -EINVAL;
0635     }
0636 
0637     return 0;
0638 }
0639 
0640 static int soc21_common_late_init(void *handle)
0641 {
0642     return 0;
0643 }
0644 
0645 static int soc21_common_sw_init(void *handle)
0646 {
0647     return 0;
0648 }
0649 
0650 static int soc21_common_sw_fini(void *handle)
0651 {
0652     return 0;
0653 }
0654 
0655 static int soc21_common_hw_init(void *handle)
0656 {
0657     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0658 
0659     /* enable pcie gen2/3 link */
0660     soc21_pcie_gen3_enable(adev);
0661     /* enable aspm */
0662     soc21_program_aspm(adev);
0663     /* setup nbio registers */
0664     adev->nbio.funcs->init_registers(adev);
0665     /* remap HDP registers to a hole in mmio space,
0666      * for the purpose of expose those registers
0667      * to process space
0668      */
0669     if (adev->nbio.funcs->remap_hdp_registers)
0670         adev->nbio.funcs->remap_hdp_registers(adev);
0671     /* enable the doorbell aperture */
0672     soc21_enable_doorbell_aperture(adev, true);
0673 
0674     return 0;
0675 }
0676 
0677 static int soc21_common_hw_fini(void *handle)
0678 {
0679     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0680 
0681     /* disable the doorbell aperture */
0682     soc21_enable_doorbell_aperture(adev, false);
0683 
0684     return 0;
0685 }
0686 
0687 static int soc21_common_suspend(void *handle)
0688 {
0689     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0690 
0691     return soc21_common_hw_fini(adev);
0692 }
0693 
0694 static int soc21_common_resume(void *handle)
0695 {
0696     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0697 
0698     return soc21_common_hw_init(adev);
0699 }
0700 
0701 static bool soc21_common_is_idle(void *handle)
0702 {
0703     return true;
0704 }
0705 
0706 static int soc21_common_wait_for_idle(void *handle)
0707 {
0708     return 0;
0709 }
0710 
0711 static int soc21_common_soft_reset(void *handle)
0712 {
0713     return 0;
0714 }
0715 
0716 static int soc21_common_set_clockgating_state(void *handle,
0717                        enum amd_clockgating_state state)
0718 {
0719     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0720 
0721     switch (adev->ip_versions[NBIO_HWIP][0]) {
0722     case IP_VERSION(4, 3, 0):
0723     case IP_VERSION(4, 3, 1):
0724     case IP_VERSION(7, 7, 0):
0725         adev->nbio.funcs->update_medium_grain_clock_gating(adev,
0726                 state == AMD_CG_STATE_GATE);
0727         adev->nbio.funcs->update_medium_grain_light_sleep(adev,
0728                 state == AMD_CG_STATE_GATE);
0729         adev->hdp.funcs->update_clock_gating(adev,
0730                 state == AMD_CG_STATE_GATE);
0731         break;
0732     default:
0733         break;
0734     }
0735     return 0;
0736 }
0737 
0738 static int soc21_common_set_powergating_state(void *handle,
0739                        enum amd_powergating_state state)
0740 {
0741     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0742 
0743     switch (adev->ip_versions[LSDMA_HWIP][0]) {
0744     case IP_VERSION(6, 0, 0):
0745     case IP_VERSION(6, 0, 2):
0746         adev->lsdma.funcs->update_memory_power_gating(adev,
0747                 state == AMD_PG_STATE_GATE);
0748         break;
0749     default:
0750         break;
0751     }
0752 
0753     return 0;
0754 }
0755 
0756 static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
0757 {
0758     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0759 
0760     adev->nbio.funcs->get_clockgating_state(adev, flags);
0761 
0762     adev->hdp.funcs->get_clock_gating_state(adev, flags);
0763 
0764     return;
0765 }
0766 
0767 static const struct amd_ip_funcs soc21_common_ip_funcs = {
0768     .name = "soc21_common",
0769     .early_init = soc21_common_early_init,
0770     .late_init = soc21_common_late_init,
0771     .sw_init = soc21_common_sw_init,
0772     .sw_fini = soc21_common_sw_fini,
0773     .hw_init = soc21_common_hw_init,
0774     .hw_fini = soc21_common_hw_fini,
0775     .suspend = soc21_common_suspend,
0776     .resume = soc21_common_resume,
0777     .is_idle = soc21_common_is_idle,
0778     .wait_for_idle = soc21_common_wait_for_idle,
0779     .soft_reset = soc21_common_soft_reset,
0780     .set_clockgating_state = soc21_common_set_clockgating_state,
0781     .set_powergating_state = soc21_common_set_powergating_state,
0782     .get_clockgating_state = soc21_common_get_clockgating_state,
0783 };
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