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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef __SOC15_COMMON_H__
0025 #define __SOC15_COMMON_H__
0026 
0027 /* Register Access Macros */
0028 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
0029 
0030 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
0031     ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
0032      amdgpu_sriov_wreg(adev, reg, value, flag, hwip) : \
0033      WREG32(reg, value))
0034 
0035 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
0036     ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
0037      amdgpu_sriov_rreg(adev, reg, flag, hwip) : \
0038      RREG32(reg))
0039 
0040 #define WREG32_FIELD15(ip, idx, reg, field, val)    \
0041      __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,   \
0042                 (__RREG32_SOC15_RLC__( \
0043                     adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
0044                     0, ip##_HWIP) & \
0045                 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
0046                   0, ip##_HWIP)
0047 
0048 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val)        \
0049     __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name,   \
0050             (__RREG32_SOC15_RLC__( \
0051                     adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
0052                     0, ip##_HWIP) & \
0053                     ~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \
0054             0, ip##_HWIP)
0055 
0056 #define RREG32_SOC15(ip, inst, reg) \
0057     __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
0058              0, ip##_HWIP)
0059 
0060 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)
0061 
0062 #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
0063 
0064 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
0065     __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
0066              AMDGPU_REGS_NO_KIQ, ip##_HWIP)
0067 
0068 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
0069      __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP)
0070 
0071 #define WREG32_SOC15(ip, inst, reg, value) \
0072      __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
0073               value, 0, ip##_HWIP)
0074 
0075 #define WREG32_SOC15_IP(ip, reg, value) \
0076      __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
0077 
0078 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
0079      __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
0080 
0081 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
0082     __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
0083                  value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
0084 
0085 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
0086      __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
0087               value, 0, ip##_HWIP)
0088 
0089 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
0090 ({  int ret = 0;                        \
0091     do {                            \
0092         uint32_t old_ = 0;              \
0093         uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
0094         uint32_t loop = adev->usec_timeout;     \
0095         ret = 0;                    \
0096         while ((tmp_ & (mask)) != (expected_value)) {   \
0097             if (old_ != tmp_) {         \
0098                 loop = adev->usec_timeout;  \
0099                 old_ = tmp_;            \
0100             } else                  \
0101                 udelay(1);          \
0102             tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
0103             loop--;                 \
0104             if (!loop) {                \
0105                 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
0106                       inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
0107                 ret = -ETIMEDOUT;       \
0108                 break;              \
0109             }                   \
0110         }                       \
0111     } while (0);                        \
0112     ret;                            \
0113 })
0114 
0115 #define WREG32_RLC(reg, value) \
0116     __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
0117 
0118 #define WREG32_RLC_EX(prefix, reg, value) \
0119     do {                            \
0120         if (amdgpu_sriov_fullaccess(adev)) {    \
0121             uint32_t i = 0; \
0122             uint32_t retries = 50000;   \
0123             uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0;   \
0124             uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1;   \
0125             uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT;  \
0126             WREG32(r0, value);  \
0127             WREG32(r1, (reg | 0x80000000)); \
0128             WREG32(spare_int, 0x1); \
0129             for (i = 0; i < retries; i++) { \
0130                 u32 tmp = RREG32(r1);   \
0131                 if (!(tmp & 0x80000000))    \
0132                     break;  \
0133                 udelay(10); \
0134             }   \
0135             if (i >= retries)   \
0136                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \
0137         } else {    \
0138             WREG32(reg, value); \
0139         }   \
0140     } while (0)
0141 
0142 /* shadow the registers in the callback function */
0143 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
0144     __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)
0145 
0146 /* for GC only */
0147 #define RREG32_RLC(reg) \
0148     __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
0149 
0150 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \
0151     __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
0152 
0153 #define RREG32_RLC_NO_KIQ(reg, hwip) \
0154     __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
0155 
0156 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
0157     do {                            \
0158         uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
0159         if (amdgpu_sriov_fullaccess(adev)) {    \
0160             uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2;   \
0161             uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3;   \
0162             uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL;   \
0163             uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX;   \
0164             if (target_reg == grbm_cntl) \
0165                 WREG32(r2, value);  \
0166             else if (target_reg == grbm_idx) \
0167                 WREG32(r3, value);  \
0168             WREG32(target_reg, value);  \
0169         } else {    \
0170             WREG32(target_reg, value); \
0171         }   \
0172     } while (0)
0173 
0174 #define RREG32_SOC15_RLC(ip, inst, reg) \
0175     __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP)
0176 
0177 #define WREG32_SOC15_RLC(ip, inst, reg, value) \
0178     do {                            \
0179         uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
0180         __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \
0181     } while (0)
0182 
0183 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \
0184     do {                            \
0185             uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
0186             WREG32_RLC_EX(prefix, target_reg, value); \
0187     } while (0)
0188 
0189 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \
0190     __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
0191                  (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
0192                            AMDGPU_REGS_RLC, ip##_HWIP) & \
0193                   ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
0194                  AMDGPU_REGS_RLC, ip##_HWIP)
0195 
0196 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
0197     __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP)
0198 
0199 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
0200     __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP)
0201 
0202 #endif
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