amd/amdgpu/soc15.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __SOC15_H__
0025 #define __SOC15_H__
0026
0027 #include "nbio_v6_1.h"
0028 #include "nbio_v7_0.h"
0029 #include "nbio_v7_4.h"
0030
0031 extern const struct amdgpu_ip_block_version vega10_common_ip_block;
0032
0033 #define SOC15_FLUSH_GPU_TLB_NUM_WREG        6
0034 #define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT    3
0035
0036 struct soc15_reg_golden {
0037     u32 hwip;
0038     u32 instance;
0039     u32 segment;
0040     u32 reg;
0041     u32 and_mask;
0042     u32 or_mask;
0043 };
0044
0045 struct soc15_reg_rlcg {
0046     u32 hwip;
0047     u32 instance;
0048     u32 segment;
0049     u32 reg;
0050 };
0051
0052 struct soc15_reg {
0053     uint32_t hwip;
0054     uint32_t inst;
0055     uint32_t seg;
0056     uint32_t reg_offset;
0057 };
0058
0059 struct soc15_reg_entry {
0060     uint32_t hwip;
0061     uint32_t inst;
0062     uint32_t seg;
0063     uint32_t reg_offset;
0064     uint32_t reg_value;
0065     uint32_t se_num;
0066     uint32_t instance;
0067 };
0068
0069 struct soc15_allowed_register_entry {
0070     uint32_t hwip;
0071     uint32_t inst;
0072     uint32_t seg;
0073     uint32_t reg_offset;
0074     bool grbm_indexed;
0075 };
0076
0077 struct soc15_ras_field_entry {
0078     const char *name;
0079     uint32_t hwip;
0080     uint32_t inst;
0081     uint32_t seg;
0082     uint32_t reg_offset;
0083     uint32_t sec_count_mask;
0084     uint32_t sec_count_shift;
0085     uint32_t ded_count_mask;
0086     uint32_t ded_count_shift;
0087 };
0088
0089 #define SOC15_REG_ENTRY(ip, inst, reg)  ip##_HWIP, inst, reg##_BASE_IDX, reg
0090
0091 #define SOC15_REG_ENTRY_OFFSET(entry)   (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
0092
0093 #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
0094     { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
0095
0096 #define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
0097
0098 #define SOC15_REG_FIELD_VAL(val, mask, shift)   (((val) & mask) >> shift)
0099
0100 #define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
0101
0102 void soc15_grbm_select(struct amdgpu_device *adev,
0103             u32 me, u32 pipe, u32 queue, u32 vmid);
0104 void soc15_set_virt_ops(struct amdgpu_device *adev);
0105
0106 void soc15_program_register_sequence(struct amdgpu_device *adev,
0107                          const struct soc15_reg_golden *registers,
0108                          const u32 array_size);
0109
0110 int vega10_reg_base_init(struct amdgpu_device *adev);
0111 int vega20_reg_base_init(struct amdgpu_device *adev);
0112 int arct_reg_base_init(struct amdgpu_device *adev);
0113 int aldebaran_reg_base_init(struct amdgpu_device *adev);
0114
0115 void vega10_doorbell_index_init(struct amdgpu_device *adev);
0116 void vega20_doorbell_index_init(struct amdgpu_device *adev);
0117 #endif