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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/firmware.h>
0024 #include <linux/slab.h>
0025 #include <linux/module.h>
0026 #include <linux/pci.h>
0027 
0028 #include <drm/amdgpu_drm.h>
0029 
0030 #include "amdgpu.h"
0031 #include "amdgpu_atombios.h"
0032 #include "amdgpu_ih.h"
0033 #include "amdgpu_uvd.h"
0034 #include "amdgpu_vce.h"
0035 #include "amdgpu_ucode.h"
0036 #include "amdgpu_psp.h"
0037 #include "atom.h"
0038 #include "amd_pcie.h"
0039 
0040 #include "uvd/uvd_7_0_offset.h"
0041 #include "gc/gc_9_0_offset.h"
0042 #include "gc/gc_9_0_sh_mask.h"
0043 #include "sdma0/sdma0_4_0_offset.h"
0044 #include "sdma1/sdma1_4_0_offset.h"
0045 #include "nbio/nbio_7_0_default.h"
0046 #include "nbio/nbio_7_0_offset.h"
0047 #include "nbio/nbio_7_0_sh_mask.h"
0048 #include "nbio/nbio_7_0_smn.h"
0049 #include "mp/mp_9_0_offset.h"
0050 
0051 #include "soc15.h"
0052 #include "soc15_common.h"
0053 #include "gfx_v9_0.h"
0054 #include "gmc_v9_0.h"
0055 #include "gfxhub_v1_0.h"
0056 #include "mmhub_v1_0.h"
0057 #include "df_v1_7.h"
0058 #include "df_v3_6.h"
0059 #include "nbio_v6_1.h"
0060 #include "nbio_v7_0.h"
0061 #include "nbio_v7_4.h"
0062 #include "hdp_v4_0.h"
0063 #include "vega10_ih.h"
0064 #include "vega20_ih.h"
0065 #include "navi10_ih.h"
0066 #include "sdma_v4_0.h"
0067 #include "uvd_v7_0.h"
0068 #include "vce_v4_0.h"
0069 #include "vcn_v1_0.h"
0070 #include "vcn_v2_0.h"
0071 #include "jpeg_v2_0.h"
0072 #include "vcn_v2_5.h"
0073 #include "jpeg_v2_5.h"
0074 #include "smuio_v9_0.h"
0075 #include "smuio_v11_0.h"
0076 #include "smuio_v13_0.h"
0077 #include "amdgpu_vkms.h"
0078 #include "mxgpu_ai.h"
0079 #include "amdgpu_ras.h"
0080 #include "amdgpu_xgmi.h"
0081 #include <uapi/linux/kfd_ioctl.h>
0082 
0083 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
0084 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
0085 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
0086 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
0087 
0088 static const struct amd_ip_funcs soc15_common_ip_funcs;
0089 
0090 /* Vega, Raven, Arcturus */
0091 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
0092 {
0093     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
0094     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
0095 };
0096 
0097 static const struct amdgpu_video_codecs vega_video_codecs_encode =
0098 {
0099     .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
0100     .codec_array = vega_video_codecs_encode_array,
0101 };
0102 
0103 /* Vega */
0104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
0105 {
0106     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
0107     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
0108     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0109     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
0110     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
0111     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0112 };
0113 
0114 static const struct amdgpu_video_codecs vega_video_codecs_decode =
0115 {
0116     .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
0117     .codec_array = vega_video_codecs_decode_array,
0118 };
0119 
0120 /* Raven */
0121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
0122 {
0123     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
0124     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
0125     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0126     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
0127     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
0128     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0129     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
0130 };
0131 
0132 static const struct amdgpu_video_codecs rv_video_codecs_decode =
0133 {
0134     .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
0135     .codec_array = rv_video_codecs_decode_array,
0136 };
0137 
0138 /* Renoir, Arcturus */
0139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
0140 {
0141     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
0142     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
0143     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0144     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
0145     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
0146     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0147     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
0148 };
0149 
0150 static const struct amdgpu_video_codecs rn_video_codecs_decode =
0151 {
0152     .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
0153     .codec_array = rn_video_codecs_decode_array,
0154 };
0155 
0156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
0157                     const struct amdgpu_video_codecs **codecs)
0158 {
0159     if (adev->ip_versions[VCE_HWIP][0]) {
0160         switch (adev->ip_versions[VCE_HWIP][0]) {
0161         case IP_VERSION(4, 0, 0):
0162         case IP_VERSION(4, 1, 0):
0163             if (encode)
0164                 *codecs = &vega_video_codecs_encode;
0165             else
0166                 *codecs = &vega_video_codecs_decode;
0167             return 0;
0168         default:
0169             return -EINVAL;
0170         }
0171     } else {
0172         switch (adev->ip_versions[UVD_HWIP][0]) {
0173         case IP_VERSION(1, 0, 0):
0174         case IP_VERSION(1, 0, 1):
0175             if (encode)
0176                 *codecs = &vega_video_codecs_encode;
0177             else
0178                 *codecs = &rv_video_codecs_decode;
0179             return 0;
0180         case IP_VERSION(2, 5, 0):
0181         case IP_VERSION(2, 6, 0):
0182         case IP_VERSION(2, 2, 0):
0183             if (encode)
0184                 *codecs = &vega_video_codecs_encode;
0185             else
0186                 *codecs = &rn_video_codecs_decode;
0187             return 0;
0188         default:
0189             return -EINVAL;
0190         }
0191     }
0192 }
0193 
0194 /*
0195  * Indirect registers accessor
0196  */
0197 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
0198 {
0199     unsigned long address, data;
0200     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0201     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0202 
0203     return amdgpu_device_indirect_rreg(adev, address, data, reg);
0204 }
0205 
0206 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0207 {
0208     unsigned long address, data;
0209 
0210     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0211     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0212 
0213     amdgpu_device_indirect_wreg(adev, address, data, reg, v);
0214 }
0215 
0216 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
0217 {
0218     unsigned long address, data;
0219     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0220     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0221 
0222     return amdgpu_device_indirect_rreg64(adev, address, data, reg);
0223 }
0224 
0225 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
0226 {
0227     unsigned long address, data;
0228 
0229     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0230     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0231 
0232     amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
0233 }
0234 
0235 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
0236 {
0237     unsigned long flags, address, data;
0238     u32 r;
0239 
0240     address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
0241     data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
0242 
0243     spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
0244     WREG32(address, ((reg) & 0x1ff));
0245     r = RREG32(data);
0246     spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
0247     return r;
0248 }
0249 
0250 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0251 {
0252     unsigned long flags, address, data;
0253 
0254     address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
0255     data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
0256 
0257     spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
0258     WREG32(address, ((reg) & 0x1ff));
0259     WREG32(data, (v));
0260     spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
0261 }
0262 
0263 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
0264 {
0265     unsigned long flags, address, data;
0266     u32 r;
0267 
0268     address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
0269     data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
0270 
0271     spin_lock_irqsave(&adev->didt_idx_lock, flags);
0272     WREG32(address, (reg));
0273     r = RREG32(data);
0274     spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
0275     return r;
0276 }
0277 
0278 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0279 {
0280     unsigned long flags, address, data;
0281 
0282     address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
0283     data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
0284 
0285     spin_lock_irqsave(&adev->didt_idx_lock, flags);
0286     WREG32(address, (reg));
0287     WREG32(data, (v));
0288     spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
0289 }
0290 
0291 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
0292 {
0293     unsigned long flags;
0294     u32 r;
0295 
0296     spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
0297     WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
0298     r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
0299     spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
0300     return r;
0301 }
0302 
0303 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0304 {
0305     unsigned long flags;
0306 
0307     spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
0308     WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
0309     WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
0310     spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
0311 }
0312 
0313 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
0314 {
0315     unsigned long flags;
0316     u32 r;
0317 
0318     spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
0319     WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
0320     r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
0321     spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
0322     return r;
0323 }
0324 
0325 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0326 {
0327     unsigned long flags;
0328 
0329     spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
0330     WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
0331     WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
0332     spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
0333 }
0334 
0335 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
0336 {
0337     return adev->nbio.funcs->get_memsize(adev);
0338 }
0339 
0340 static u32 soc15_get_xclk(struct amdgpu_device *adev)
0341 {
0342     u32 reference_clock = adev->clock.spll.reference_freq;
0343 
0344     if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
0345         adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
0346         return 10000;
0347     if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
0348         adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
0349         return reference_clock / 4;
0350 
0351     return reference_clock;
0352 }
0353 
0354 
0355 void soc15_grbm_select(struct amdgpu_device *adev,
0356              u32 me, u32 pipe, u32 queue, u32 vmid)
0357 {
0358     u32 grbm_gfx_cntl = 0;
0359     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
0360     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
0361     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
0362     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
0363 
0364     WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
0365 }
0366 
0367 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
0368 {
0369     /* todo */
0370 }
0371 
0372 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
0373 {
0374     /* todo */
0375     return false;
0376 }
0377 
0378 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
0379     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
0380     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
0381     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
0382     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
0383     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
0384     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
0385     { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
0386     { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
0387     { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
0388     { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
0389     { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
0390     { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
0391     { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
0392     { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
0393     { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
0394     { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
0395     { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
0396     { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
0397     { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
0398     { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
0399 };
0400 
0401 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
0402                      u32 sh_num, u32 reg_offset)
0403 {
0404     uint32_t val;
0405 
0406     mutex_lock(&adev->grbm_idx_mutex);
0407     if (se_num != 0xffffffff || sh_num != 0xffffffff)
0408         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
0409 
0410     val = RREG32(reg_offset);
0411 
0412     if (se_num != 0xffffffff || sh_num != 0xffffffff)
0413         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
0414     mutex_unlock(&adev->grbm_idx_mutex);
0415     return val;
0416 }
0417 
0418 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
0419                      bool indexed, u32 se_num,
0420                      u32 sh_num, u32 reg_offset)
0421 {
0422     if (indexed) {
0423         return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
0424     } else {
0425         if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
0426             return adev->gfx.config.gb_addr_config;
0427         else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
0428             return adev->gfx.config.db_debug2;
0429         return RREG32(reg_offset);
0430     }
0431 }
0432 
0433 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
0434                 u32 sh_num, u32 reg_offset, u32 *value)
0435 {
0436     uint32_t i;
0437     struct soc15_allowed_register_entry  *en;
0438 
0439     *value = 0;
0440     for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
0441         en = &soc15_allowed_read_registers[i];
0442         if (adev->reg_offset[en->hwip][en->inst] &&
0443             reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
0444                     + en->reg_offset))
0445             continue;
0446 
0447         *value = soc15_get_register_value(adev,
0448                           soc15_allowed_read_registers[i].grbm_indexed,
0449                           se_num, sh_num, reg_offset);
0450         return 0;
0451     }
0452     return -EINVAL;
0453 }
0454 
0455 
0456 /**
0457  * soc15_program_register_sequence - program an array of registers.
0458  *
0459  * @adev: amdgpu_device pointer
0460  * @regs: pointer to the register array
0461  * @array_size: size of the register array
0462  *
0463  * Programs an array or registers with and and or masks.
0464  * This is a helper for setting golden registers.
0465  */
0466 
0467 void soc15_program_register_sequence(struct amdgpu_device *adev,
0468                          const struct soc15_reg_golden *regs,
0469                          const u32 array_size)
0470 {
0471     const struct soc15_reg_golden *entry;
0472     u32 tmp, reg;
0473     int i;
0474 
0475     for (i = 0; i < array_size; ++i) {
0476         entry = &regs[i];
0477         reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
0478 
0479         if (entry->and_mask == 0xffffffff) {
0480             tmp = entry->or_mask;
0481         } else {
0482             tmp = (entry->hwip == GC_HWIP) ?
0483                 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
0484 
0485             tmp &= ~(entry->and_mask);
0486             tmp |= (entry->or_mask & entry->and_mask);
0487         }
0488 
0489         if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
0490             reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
0491             reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
0492             reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
0493             WREG32_RLC(reg, tmp);
0494         else
0495             (entry->hwip == GC_HWIP) ?
0496                 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
0497 
0498     }
0499 
0500 }
0501 
0502 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
0503 {
0504     struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
0505     int ret = 0;
0506 
0507     /* avoid NBIF got stuck when do RAS recovery in BACO reset */
0508     if (ras && adev->ras_enabled)
0509         adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
0510 
0511     ret = amdgpu_dpm_baco_reset(adev);
0512     if (ret)
0513         return ret;
0514 
0515     /* re-enable doorbell interrupt after BACO exit */
0516     if (ras && adev->ras_enabled)
0517         adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
0518 
0519     return 0;
0520 }
0521 
0522 static enum amd_reset_method
0523 soc15_asic_reset_method(struct amdgpu_device *adev)
0524 {
0525     bool baco_reset = false;
0526     bool connected_to_cpu = false;
0527     struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
0528 
0529         if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
0530                 connected_to_cpu = true;
0531 
0532     if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
0533         amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
0534         amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
0535         amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
0536         /* If connected to cpu, driver only support mode2 */
0537                 if (connected_to_cpu)
0538                         return AMD_RESET_METHOD_MODE2;
0539                 return amdgpu_reset_method;
0540         }
0541 
0542     if (amdgpu_reset_method != -1)
0543         dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
0544                   amdgpu_reset_method);
0545 
0546     switch (adev->ip_versions[MP1_HWIP][0]) {
0547     case IP_VERSION(10, 0, 0):
0548     case IP_VERSION(10, 0, 1):
0549     case IP_VERSION(12, 0, 0):
0550     case IP_VERSION(12, 0, 1):
0551         return AMD_RESET_METHOD_MODE2;
0552     case IP_VERSION(9, 0, 0):
0553     case IP_VERSION(11, 0, 2):
0554         if (adev->asic_type == CHIP_VEGA20) {
0555             if (adev->psp.sos.fw_version >= 0x80067)
0556                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
0557             /*
0558              * 1. PMFW version > 0x284300: all cases use baco
0559              * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
0560              */
0561             if (ras && adev->ras_enabled &&
0562                 adev->pm.fw_version <= 0x283400)
0563                 baco_reset = false;
0564         } else {
0565             baco_reset = amdgpu_dpm_is_baco_supported(adev);
0566         }
0567         break;
0568     case IP_VERSION(13, 0, 2):
0569          /*
0570          * 1.connected to cpu: driver issue mode2 reset
0571          * 2.discret gpu: driver issue mode1 reset
0572          */
0573         if (connected_to_cpu)
0574             return AMD_RESET_METHOD_MODE2;
0575         break;
0576     default:
0577         break;
0578     }
0579 
0580     if (baco_reset)
0581         return AMD_RESET_METHOD_BACO;
0582     else
0583         return AMD_RESET_METHOD_MODE1;
0584 }
0585 
0586 static int soc15_asic_reset(struct amdgpu_device *adev)
0587 {
0588     /* original raven doesn't have full asic reset */
0589     if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
0590         (adev->apu_flags & AMD_APU_IS_RAVEN2))
0591         return 0;
0592 
0593     switch (soc15_asic_reset_method(adev)) {
0594     case AMD_RESET_METHOD_PCI:
0595         dev_info(adev->dev, "PCI reset\n");
0596         return amdgpu_device_pci_reset(adev);
0597     case AMD_RESET_METHOD_BACO:
0598         dev_info(adev->dev, "BACO reset\n");
0599         return soc15_asic_baco_reset(adev);
0600     case AMD_RESET_METHOD_MODE2:
0601         dev_info(adev->dev, "MODE2 reset\n");
0602         return amdgpu_dpm_mode2_reset(adev);
0603     default:
0604         dev_info(adev->dev, "MODE1 reset\n");
0605         return amdgpu_device_mode1_reset(adev);
0606     }
0607 }
0608 
0609 static bool soc15_supports_baco(struct amdgpu_device *adev)
0610 {
0611     switch (adev->ip_versions[MP1_HWIP][0]) {
0612     case IP_VERSION(9, 0, 0):
0613     case IP_VERSION(11, 0, 2):
0614         if (adev->asic_type == CHIP_VEGA20) {
0615             if (adev->psp.sos.fw_version >= 0x80067)
0616                 return amdgpu_dpm_is_baco_supported(adev);
0617             return false;
0618         } else {
0619             return amdgpu_dpm_is_baco_supported(adev);
0620         }
0621         break;
0622     default:
0623         return false;
0624     }
0625 }
0626 
0627 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
0628             u32 cntl_reg, u32 status_reg)
0629 {
0630     return 0;
0631 }*/
0632 
0633 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
0634 {
0635     /*int r;
0636 
0637     r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
0638     if (r)
0639         return r;
0640 
0641     r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
0642     */
0643     return 0;
0644 }
0645 
0646 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
0647 {
0648     /* todo */
0649 
0650     return 0;
0651 }
0652 
0653 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
0654 {
0655     if (pci_is_root_bus(adev->pdev->bus))
0656         return;
0657 
0658     if (amdgpu_pcie_gen2 == 0)
0659         return;
0660 
0661     if (adev->flags & AMD_IS_APU)
0662         return;
0663 
0664     if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
0665                     CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
0666         return;
0667 
0668     /* todo */
0669 }
0670 
0671 static void soc15_program_aspm(struct amdgpu_device *adev)
0672 {
0673     if (!amdgpu_device_should_use_aspm(adev))
0674         return;
0675 
0676     if (!(adev->flags & AMD_IS_APU) &&
0677         (adev->nbio.funcs->program_aspm))
0678         adev->nbio.funcs->program_aspm(adev);
0679 }
0680 
0681 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
0682                        bool enable)
0683 {
0684     adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
0685     adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
0686 }
0687 
0688 const struct amdgpu_ip_block_version vega10_common_ip_block =
0689 {
0690     .type = AMD_IP_BLOCK_TYPE_COMMON,
0691     .major = 2,
0692     .minor = 0,
0693     .rev = 0,
0694     .funcs = &soc15_common_ip_funcs,
0695 };
0696 
0697 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
0698 {
0699     return adev->nbio.funcs->get_rev_id(adev);
0700 }
0701 
0702 static void soc15_reg_base_init(struct amdgpu_device *adev)
0703 {
0704     /* Set IP register base before any HW register access */
0705     switch (adev->asic_type) {
0706     case CHIP_VEGA10:
0707     case CHIP_VEGA12:
0708     case CHIP_RAVEN:
0709     case CHIP_RENOIR:
0710         vega10_reg_base_init(adev);
0711         break;
0712     case CHIP_VEGA20:
0713         vega20_reg_base_init(adev);
0714         break;
0715     case CHIP_ARCTURUS:
0716         arct_reg_base_init(adev);
0717         break;
0718     case CHIP_ALDEBARAN:
0719         aldebaran_reg_base_init(adev);
0720         break;
0721     default:
0722         DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
0723         break;
0724     }
0725 }
0726 
0727 void soc15_set_virt_ops(struct amdgpu_device *adev)
0728 {
0729     adev->virt.ops = &xgpu_ai_virt_ops;
0730 
0731     /* init soc15 reg base early enough so we can
0732      * request request full access for sriov before
0733      * set_ip_blocks. */
0734     soc15_reg_base_init(adev);
0735 }
0736 
0737 static bool soc15_need_full_reset(struct amdgpu_device *adev)
0738 {
0739     /* change this when we implement soft reset */
0740     return true;
0741 }
0742 
0743 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
0744                  uint64_t *count1)
0745 {
0746     uint32_t perfctr = 0;
0747     uint64_t cnt0_of, cnt1_of;
0748     int tmp;
0749 
0750     /* This reports 0 on APUs, so return to avoid writing/reading registers
0751      * that may or may not be different from their GPU counterparts
0752      */
0753     if (adev->flags & AMD_IS_APU)
0754         return;
0755 
0756     /* Set the 2 events that we wish to watch, defined above */
0757     /* Reg 40 is # received msgs */
0758     /* Reg 104 is # of posted requests sent */
0759     perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
0760     perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
0761 
0762     /* Write to enable desired perf counters */
0763     WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
0764     /* Zero out and enable the perf counters
0765      * Write 0x5:
0766      * Bit 0 = Start all counters(1)
0767      * Bit 2 = Global counter reset enable(1)
0768      */
0769     WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
0770 
0771     msleep(1000);
0772 
0773     /* Load the shadow and disable the perf counters
0774      * Write 0x2:
0775      * Bit 0 = Stop counters(0)
0776      * Bit 1 = Load the shadow counters(1)
0777      */
0778     WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
0779 
0780     /* Read register values to get any >32bit overflow */
0781     tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
0782     cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
0783     cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
0784 
0785     /* Get the values and add the overflow */
0786     *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
0787     *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
0788 }
0789 
0790 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
0791                  uint64_t *count1)
0792 {
0793     uint32_t perfctr = 0;
0794     uint64_t cnt0_of, cnt1_of;
0795     int tmp;
0796 
0797     /* This reports 0 on APUs, so return to avoid writing/reading registers
0798      * that may or may not be different from their GPU counterparts
0799      */
0800     if (adev->flags & AMD_IS_APU)
0801         return;
0802 
0803     /* Set the 2 events that we wish to watch, defined above */
0804     /* Reg 40 is # received msgs */
0805     /* Reg 108 is # of posted requests sent on VG20 */
0806     perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
0807                 EVENT0_SEL, 40);
0808     perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
0809                 EVENT1_SEL, 108);
0810 
0811     /* Write to enable desired perf counters */
0812     WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
0813     /* Zero out and enable the perf counters
0814      * Write 0x5:
0815      * Bit 0 = Start all counters(1)
0816      * Bit 2 = Global counter reset enable(1)
0817      */
0818     WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
0819 
0820     msleep(1000);
0821 
0822     /* Load the shadow and disable the perf counters
0823      * Write 0x2:
0824      * Bit 0 = Stop counters(0)
0825      * Bit 1 = Load the shadow counters(1)
0826      */
0827     WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
0828 
0829     /* Read register values to get any >32bit overflow */
0830     tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
0831     cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
0832     cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
0833 
0834     /* Get the values and add the overflow */
0835     *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
0836     *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
0837 }
0838 
0839 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
0840 {
0841     u32 sol_reg;
0842 
0843     /* CP hangs in IGT reloading test on RN, reset to WA */
0844     if (adev->asic_type == CHIP_RENOIR)
0845         return true;
0846 
0847     /* Just return false for soc15 GPUs.  Reset does not seem to
0848      * be necessary.
0849      */
0850     if (!amdgpu_passthrough(adev))
0851         return false;
0852 
0853     if (adev->flags & AMD_IS_APU)
0854         return false;
0855 
0856     /* Check sOS sign of life register to confirm sys driver and sOS
0857      * are already been loaded.
0858      */
0859     sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
0860     if (sol_reg)
0861         return true;
0862 
0863     return false;
0864 }
0865 
0866 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
0867 {
0868     uint64_t nak_r, nak_g;
0869 
0870     /* Get the number of NAKs received and generated */
0871     nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
0872     nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
0873 
0874     /* Add the total number of NAKs, i.e the number of replays */
0875     return (nak_r + nak_g);
0876 }
0877 
0878 static void soc15_pre_asic_init(struct amdgpu_device *adev)
0879 {
0880     gmc_v9_0_restore_registers(adev);
0881 }
0882 
0883 static const struct amdgpu_asic_funcs soc15_asic_funcs =
0884 {
0885     .read_disabled_bios = &soc15_read_disabled_bios,
0886     .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
0887     .read_register = &soc15_read_register,
0888     .reset = &soc15_asic_reset,
0889     .reset_method = &soc15_asic_reset_method,
0890     .set_vga_state = &soc15_vga_set_state,
0891     .get_xclk = &soc15_get_xclk,
0892     .set_uvd_clocks = &soc15_set_uvd_clocks,
0893     .set_vce_clocks = &soc15_set_vce_clocks,
0894     .get_config_memsize = &soc15_get_config_memsize,
0895     .need_full_reset = &soc15_need_full_reset,
0896     .init_doorbell_index = &vega10_doorbell_index_init,
0897     .get_pcie_usage = &soc15_get_pcie_usage,
0898     .need_reset_on_init = &soc15_need_reset_on_init,
0899     .get_pcie_replay_count = &soc15_get_pcie_replay_count,
0900     .supports_baco = &soc15_supports_baco,
0901     .pre_asic_init = &soc15_pre_asic_init,
0902     .query_video_codecs = &soc15_query_video_codecs,
0903 };
0904 
0905 static const struct amdgpu_asic_funcs vega20_asic_funcs =
0906 {
0907     .read_disabled_bios = &soc15_read_disabled_bios,
0908     .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
0909     .read_register = &soc15_read_register,
0910     .reset = &soc15_asic_reset,
0911     .reset_method = &soc15_asic_reset_method,
0912     .set_vga_state = &soc15_vga_set_state,
0913     .get_xclk = &soc15_get_xclk,
0914     .set_uvd_clocks = &soc15_set_uvd_clocks,
0915     .set_vce_clocks = &soc15_set_vce_clocks,
0916     .get_config_memsize = &soc15_get_config_memsize,
0917     .need_full_reset = &soc15_need_full_reset,
0918     .init_doorbell_index = &vega20_doorbell_index_init,
0919     .get_pcie_usage = &vega20_get_pcie_usage,
0920     .need_reset_on_init = &soc15_need_reset_on_init,
0921     .get_pcie_replay_count = &soc15_get_pcie_replay_count,
0922     .supports_baco = &soc15_supports_baco,
0923     .pre_asic_init = &soc15_pre_asic_init,
0924     .query_video_codecs = &soc15_query_video_codecs,
0925 };
0926 
0927 static int soc15_common_early_init(void *handle)
0928 {
0929 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
0930     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0931 
0932     if (!amdgpu_sriov_vf(adev)) {
0933         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
0934         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
0935     }
0936     adev->smc_rreg = NULL;
0937     adev->smc_wreg = NULL;
0938     adev->pcie_rreg = &soc15_pcie_rreg;
0939     adev->pcie_wreg = &soc15_pcie_wreg;
0940     adev->pcie_rreg64 = &soc15_pcie_rreg64;
0941     adev->pcie_wreg64 = &soc15_pcie_wreg64;
0942     adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
0943     adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
0944     adev->didt_rreg = &soc15_didt_rreg;
0945     adev->didt_wreg = &soc15_didt_wreg;
0946     adev->gc_cac_rreg = &soc15_gc_cac_rreg;
0947     adev->gc_cac_wreg = &soc15_gc_cac_wreg;
0948     adev->se_cac_rreg = &soc15_se_cac_rreg;
0949     adev->se_cac_wreg = &soc15_se_cac_wreg;
0950 
0951     adev->rev_id = soc15_get_rev_id(adev);
0952     adev->external_rev_id = 0xFF;
0953     /* TODO: split the GC and PG flags based on the relevant IP version for which
0954      * they are relevant.
0955      */
0956     switch (adev->ip_versions[GC_HWIP][0]) {
0957     case IP_VERSION(9, 0, 1):
0958         adev->asic_funcs = &soc15_asic_funcs;
0959         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0960             AMD_CG_SUPPORT_GFX_MGLS |
0961             AMD_CG_SUPPORT_GFX_RLC_LS |
0962             AMD_CG_SUPPORT_GFX_CP_LS |
0963             AMD_CG_SUPPORT_GFX_3D_CGCG |
0964             AMD_CG_SUPPORT_GFX_3D_CGLS |
0965             AMD_CG_SUPPORT_GFX_CGCG |
0966             AMD_CG_SUPPORT_GFX_CGLS |
0967             AMD_CG_SUPPORT_BIF_MGCG |
0968             AMD_CG_SUPPORT_BIF_LS |
0969             AMD_CG_SUPPORT_HDP_LS |
0970             AMD_CG_SUPPORT_DRM_MGCG |
0971             AMD_CG_SUPPORT_DRM_LS |
0972             AMD_CG_SUPPORT_ROM_MGCG |
0973             AMD_CG_SUPPORT_DF_MGCG |
0974             AMD_CG_SUPPORT_SDMA_MGCG |
0975             AMD_CG_SUPPORT_SDMA_LS |
0976             AMD_CG_SUPPORT_MC_MGCG |
0977             AMD_CG_SUPPORT_MC_LS;
0978         adev->pg_flags = 0;
0979         adev->external_rev_id = 0x1;
0980         break;
0981     case IP_VERSION(9, 2, 1):
0982         adev->asic_funcs = &soc15_asic_funcs;
0983         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0984             AMD_CG_SUPPORT_GFX_MGLS |
0985             AMD_CG_SUPPORT_GFX_CGCG |
0986             AMD_CG_SUPPORT_GFX_CGLS |
0987             AMD_CG_SUPPORT_GFX_3D_CGCG |
0988             AMD_CG_SUPPORT_GFX_3D_CGLS |
0989             AMD_CG_SUPPORT_GFX_CP_LS |
0990             AMD_CG_SUPPORT_MC_LS |
0991             AMD_CG_SUPPORT_MC_MGCG |
0992             AMD_CG_SUPPORT_SDMA_MGCG |
0993             AMD_CG_SUPPORT_SDMA_LS |
0994             AMD_CG_SUPPORT_BIF_MGCG |
0995             AMD_CG_SUPPORT_BIF_LS |
0996             AMD_CG_SUPPORT_HDP_MGCG |
0997             AMD_CG_SUPPORT_HDP_LS |
0998             AMD_CG_SUPPORT_ROM_MGCG |
0999             AMD_CG_SUPPORT_VCE_MGCG |
1000             AMD_CG_SUPPORT_UVD_MGCG;
1001         adev->pg_flags = 0;
1002         adev->external_rev_id = adev->rev_id + 0x14;
1003         break;
1004     case IP_VERSION(9, 4, 0):
1005         adev->asic_funcs = &vega20_asic_funcs;
1006         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1007             AMD_CG_SUPPORT_GFX_MGLS |
1008             AMD_CG_SUPPORT_GFX_CGCG |
1009             AMD_CG_SUPPORT_GFX_CGLS |
1010             AMD_CG_SUPPORT_GFX_3D_CGCG |
1011             AMD_CG_SUPPORT_GFX_3D_CGLS |
1012             AMD_CG_SUPPORT_GFX_CP_LS |
1013             AMD_CG_SUPPORT_MC_LS |
1014             AMD_CG_SUPPORT_MC_MGCG |
1015             AMD_CG_SUPPORT_SDMA_MGCG |
1016             AMD_CG_SUPPORT_SDMA_LS |
1017             AMD_CG_SUPPORT_BIF_MGCG |
1018             AMD_CG_SUPPORT_BIF_LS |
1019             AMD_CG_SUPPORT_HDP_MGCG |
1020             AMD_CG_SUPPORT_HDP_LS |
1021             AMD_CG_SUPPORT_ROM_MGCG |
1022             AMD_CG_SUPPORT_VCE_MGCG |
1023             AMD_CG_SUPPORT_UVD_MGCG;
1024         adev->pg_flags = 0;
1025         adev->external_rev_id = adev->rev_id + 0x28;
1026         break;
1027     case IP_VERSION(9, 1, 0):
1028     case IP_VERSION(9, 2, 2):
1029         adev->asic_funcs = &soc15_asic_funcs;
1030 
1031         if (adev->rev_id >= 0x8)
1032             adev->apu_flags |= AMD_APU_IS_RAVEN2;
1033 
1034         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1035             adev->external_rev_id = adev->rev_id + 0x79;
1036         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1037             adev->external_rev_id = adev->rev_id + 0x41;
1038         else if (adev->rev_id == 1)
1039             adev->external_rev_id = adev->rev_id + 0x20;
1040         else
1041             adev->external_rev_id = adev->rev_id + 0x01;
1042 
1043         if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1044             adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1045                 AMD_CG_SUPPORT_GFX_MGLS |
1046                 AMD_CG_SUPPORT_GFX_CP_LS |
1047                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1048                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1049                 AMD_CG_SUPPORT_GFX_CGCG |
1050                 AMD_CG_SUPPORT_GFX_CGLS |
1051                 AMD_CG_SUPPORT_BIF_LS |
1052                 AMD_CG_SUPPORT_HDP_LS |
1053                 AMD_CG_SUPPORT_MC_MGCG |
1054                 AMD_CG_SUPPORT_MC_LS |
1055                 AMD_CG_SUPPORT_SDMA_MGCG |
1056                 AMD_CG_SUPPORT_SDMA_LS |
1057                 AMD_CG_SUPPORT_VCN_MGCG;
1058 
1059             adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1060         } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1061             adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1062                 AMD_CG_SUPPORT_GFX_MGLS |
1063                 AMD_CG_SUPPORT_GFX_CP_LS |
1064                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1065                 AMD_CG_SUPPORT_GFX_CGCG |
1066                 AMD_CG_SUPPORT_GFX_CGLS |
1067                 AMD_CG_SUPPORT_BIF_LS |
1068                 AMD_CG_SUPPORT_HDP_LS |
1069                 AMD_CG_SUPPORT_MC_MGCG |
1070                 AMD_CG_SUPPORT_MC_LS |
1071                 AMD_CG_SUPPORT_SDMA_MGCG |
1072                 AMD_CG_SUPPORT_SDMA_LS |
1073                 AMD_CG_SUPPORT_VCN_MGCG;
1074 
1075             /*
1076              * MMHUB PG needs to be disabled for Picasso for
1077              * stability reasons.
1078              */
1079             adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1080                 AMD_PG_SUPPORT_VCN;
1081         } else {
1082             adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1083                 AMD_CG_SUPPORT_GFX_MGLS |
1084                 AMD_CG_SUPPORT_GFX_RLC_LS |
1085                 AMD_CG_SUPPORT_GFX_CP_LS |
1086                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1087                 AMD_CG_SUPPORT_GFX_CGCG |
1088                 AMD_CG_SUPPORT_GFX_CGLS |
1089                 AMD_CG_SUPPORT_BIF_MGCG |
1090                 AMD_CG_SUPPORT_BIF_LS |
1091                 AMD_CG_SUPPORT_HDP_MGCG |
1092                 AMD_CG_SUPPORT_HDP_LS |
1093                 AMD_CG_SUPPORT_DRM_MGCG |
1094                 AMD_CG_SUPPORT_DRM_LS |
1095                 AMD_CG_SUPPORT_MC_MGCG |
1096                 AMD_CG_SUPPORT_MC_LS |
1097                 AMD_CG_SUPPORT_SDMA_MGCG |
1098                 AMD_CG_SUPPORT_SDMA_LS |
1099                 AMD_CG_SUPPORT_VCN_MGCG;
1100 
1101             adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1102         }
1103         break;
1104     case IP_VERSION(9, 4, 1):
1105         adev->asic_funcs = &vega20_asic_funcs;
1106         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1107             AMD_CG_SUPPORT_GFX_MGLS |
1108             AMD_CG_SUPPORT_GFX_CGCG |
1109             AMD_CG_SUPPORT_GFX_CGLS |
1110             AMD_CG_SUPPORT_GFX_CP_LS |
1111             AMD_CG_SUPPORT_HDP_MGCG |
1112             AMD_CG_SUPPORT_HDP_LS |
1113             AMD_CG_SUPPORT_SDMA_MGCG |
1114             AMD_CG_SUPPORT_SDMA_LS |
1115             AMD_CG_SUPPORT_MC_MGCG |
1116             AMD_CG_SUPPORT_MC_LS |
1117             AMD_CG_SUPPORT_IH_CG |
1118             AMD_CG_SUPPORT_VCN_MGCG |
1119             AMD_CG_SUPPORT_JPEG_MGCG;
1120         adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1121         adev->external_rev_id = adev->rev_id + 0x32;
1122         break;
1123     case IP_VERSION(9, 3, 0):
1124         adev->asic_funcs = &soc15_asic_funcs;
1125 
1126         if (adev->apu_flags & AMD_APU_IS_RENOIR)
1127             adev->external_rev_id = adev->rev_id + 0x91;
1128         else
1129             adev->external_rev_id = adev->rev_id + 0xa1;
1130         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1131                  AMD_CG_SUPPORT_GFX_MGLS |
1132                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1133                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1134                  AMD_CG_SUPPORT_GFX_CGCG |
1135                  AMD_CG_SUPPORT_GFX_CGLS |
1136                  AMD_CG_SUPPORT_GFX_CP_LS |
1137                  AMD_CG_SUPPORT_MC_MGCG |
1138                  AMD_CG_SUPPORT_MC_LS |
1139                  AMD_CG_SUPPORT_SDMA_MGCG |
1140                  AMD_CG_SUPPORT_SDMA_LS |
1141                  AMD_CG_SUPPORT_BIF_LS |
1142                  AMD_CG_SUPPORT_HDP_LS |
1143                  AMD_CG_SUPPORT_VCN_MGCG |
1144                  AMD_CG_SUPPORT_JPEG_MGCG |
1145                  AMD_CG_SUPPORT_IH_CG |
1146                  AMD_CG_SUPPORT_ATHUB_LS |
1147                  AMD_CG_SUPPORT_ATHUB_MGCG |
1148                  AMD_CG_SUPPORT_DF_MGCG;
1149         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1150                  AMD_PG_SUPPORT_VCN |
1151                  AMD_PG_SUPPORT_JPEG |
1152                  AMD_PG_SUPPORT_VCN_DPG;
1153         break;
1154     case IP_VERSION(9, 4, 2):
1155         adev->asic_funcs = &vega20_asic_funcs;
1156         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1157             AMD_CG_SUPPORT_GFX_MGLS |
1158             AMD_CG_SUPPORT_GFX_CP_LS |
1159             AMD_CG_SUPPORT_HDP_LS |
1160             AMD_CG_SUPPORT_SDMA_MGCG |
1161             AMD_CG_SUPPORT_SDMA_LS |
1162             AMD_CG_SUPPORT_IH_CG |
1163             AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1164         adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1165         adev->external_rev_id = adev->rev_id + 0x3c;
1166         break;
1167     default:
1168         /* FIXME: not supported yet */
1169         return -EINVAL;
1170     }
1171 
1172     if (amdgpu_sriov_vf(adev)) {
1173         amdgpu_virt_init_setting(adev);
1174         xgpu_ai_mailbox_set_irq_funcs(adev);
1175     }
1176 
1177     return 0;
1178 }
1179 
1180 static int soc15_common_late_init(void *handle)
1181 {
1182     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183 
1184     if (amdgpu_sriov_vf(adev))
1185         xgpu_ai_mailbox_get_irq(adev);
1186 
1187     return 0;
1188 }
1189 
1190 static int soc15_common_sw_init(void *handle)
1191 {
1192     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1193 
1194     if (amdgpu_sriov_vf(adev))
1195         xgpu_ai_mailbox_add_irq_id(adev);
1196 
1197     if (adev->df.funcs &&
1198         adev->df.funcs->sw_init)
1199         adev->df.funcs->sw_init(adev);
1200 
1201     return 0;
1202 }
1203 
1204 static int soc15_common_sw_fini(void *handle)
1205 {
1206     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207 
1208     if (adev->df.funcs &&
1209         adev->df.funcs->sw_fini)
1210         adev->df.funcs->sw_fini(adev);
1211     return 0;
1212 }
1213 
1214 static int soc15_common_hw_init(void *handle)
1215 {
1216     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217 
1218     /* enable pcie gen2/3 link */
1219     soc15_pcie_gen3_enable(adev);
1220     /* enable aspm */
1221     soc15_program_aspm(adev);
1222     /* setup nbio registers */
1223     adev->nbio.funcs->init_registers(adev);
1224     /* remap HDP registers to a hole in mmio space,
1225      * for the purpose of expose those registers
1226      * to process space
1227      */
1228     if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1229         adev->nbio.funcs->remap_hdp_registers(adev);
1230 
1231     /* enable the doorbell aperture */
1232     soc15_enable_doorbell_aperture(adev, true);
1233 
1234     return 0;
1235 }
1236 
1237 static int soc15_common_hw_fini(void *handle)
1238 {
1239     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240 
1241     /* disable the doorbell aperture */
1242     soc15_enable_doorbell_aperture(adev, false);
1243     if (amdgpu_sriov_vf(adev))
1244         xgpu_ai_mailbox_put_irq(adev);
1245 
1246     if (adev->nbio.ras_if &&
1247         amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1248         if (adev->nbio.ras &&
1249             adev->nbio.ras->init_ras_controller_interrupt)
1250             amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1251         if (adev->nbio.ras &&
1252             adev->nbio.ras->init_ras_err_event_athub_interrupt)
1253             amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1254     }
1255 
1256     return 0;
1257 }
1258 
1259 static int soc15_common_suspend(void *handle)
1260 {
1261     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262 
1263     return soc15_common_hw_fini(adev);
1264 }
1265 
1266 static int soc15_common_resume(void *handle)
1267 {
1268     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1269 
1270     return soc15_common_hw_init(adev);
1271 }
1272 
1273 static bool soc15_common_is_idle(void *handle)
1274 {
1275     return true;
1276 }
1277 
1278 static int soc15_common_wait_for_idle(void *handle)
1279 {
1280     return 0;
1281 }
1282 
1283 static int soc15_common_soft_reset(void *handle)
1284 {
1285     return 0;
1286 }
1287 
1288 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1289 {
1290     uint32_t def, data;
1291 
1292     def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1293 
1294     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1295         data &= ~(0x01000000 |
1296               0x02000000 |
1297               0x04000000 |
1298               0x08000000 |
1299               0x10000000 |
1300               0x20000000 |
1301               0x40000000 |
1302               0x80000000);
1303     else
1304         data |= (0x01000000 |
1305              0x02000000 |
1306              0x04000000 |
1307              0x08000000 |
1308              0x10000000 |
1309              0x20000000 |
1310              0x40000000 |
1311              0x80000000);
1312 
1313     if (def != data)
1314         WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1315 }
1316 
1317 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1318 {
1319     uint32_t def, data;
1320 
1321     def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1322 
1323     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1324         data |= 1;
1325     else
1326         data &= ~1;
1327 
1328     if (def != data)
1329         WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1330 }
1331 
1332 static int soc15_common_set_clockgating_state(void *handle,
1333                         enum amd_clockgating_state state)
1334 {
1335     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1336 
1337     if (amdgpu_sriov_vf(adev))
1338         return 0;
1339 
1340     switch (adev->ip_versions[NBIO_HWIP][0]) {
1341     case IP_VERSION(6, 1, 0):
1342     case IP_VERSION(6, 2, 0):
1343     case IP_VERSION(7, 4, 0):
1344         adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1345                 state == AMD_CG_STATE_GATE);
1346         adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1347                 state == AMD_CG_STATE_GATE);
1348         adev->hdp.funcs->update_clock_gating(adev,
1349                 state == AMD_CG_STATE_GATE);
1350         soc15_update_drm_clock_gating(adev,
1351                 state == AMD_CG_STATE_GATE);
1352         soc15_update_drm_light_sleep(adev,
1353                 state == AMD_CG_STATE_GATE);
1354         adev->smuio.funcs->update_rom_clock_gating(adev,
1355                 state == AMD_CG_STATE_GATE);
1356         adev->df.funcs->update_medium_grain_clock_gating(adev,
1357                 state == AMD_CG_STATE_GATE);
1358         break;
1359     case IP_VERSION(7, 0, 0):
1360     case IP_VERSION(7, 0, 1):
1361     case IP_VERSION(2, 5, 0):
1362         adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1363                 state == AMD_CG_STATE_GATE);
1364         adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1365                 state == AMD_CG_STATE_GATE);
1366         adev->hdp.funcs->update_clock_gating(adev,
1367                 state == AMD_CG_STATE_GATE);
1368         soc15_update_drm_clock_gating(adev,
1369                 state == AMD_CG_STATE_GATE);
1370         soc15_update_drm_light_sleep(adev,
1371                 state == AMD_CG_STATE_GATE);
1372         break;
1373     case IP_VERSION(7, 4, 1):
1374     case IP_VERSION(7, 4, 4):
1375         adev->hdp.funcs->update_clock_gating(adev,
1376                 state == AMD_CG_STATE_GATE);
1377         break;
1378     default:
1379         break;
1380     }
1381     return 0;
1382 }
1383 
1384 static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1385 {
1386     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1387     int data;
1388 
1389     if (amdgpu_sriov_vf(adev))
1390         *flags = 0;
1391 
1392     adev->nbio.funcs->get_clockgating_state(adev, flags);
1393 
1394     adev->hdp.funcs->get_clock_gating_state(adev, flags);
1395 
1396     if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1397 
1398         /* AMD_CG_SUPPORT_DRM_MGCG */
1399         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1400         if (!(data & 0x01000000))
1401             *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1402 
1403         /* AMD_CG_SUPPORT_DRM_LS */
1404         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1405         if (data & 0x1)
1406             *flags |= AMD_CG_SUPPORT_DRM_LS;
1407     }
1408 
1409     /* AMD_CG_SUPPORT_ROM_MGCG */
1410     adev->smuio.funcs->get_clock_gating_state(adev, flags);
1411 
1412     adev->df.funcs->get_clockgating_state(adev, flags);
1413 }
1414 
1415 static int soc15_common_set_powergating_state(void *handle,
1416                         enum amd_powergating_state state)
1417 {
1418     /* todo */
1419     return 0;
1420 }
1421 
1422 static const struct amd_ip_funcs soc15_common_ip_funcs = {
1423     .name = "soc15_common",
1424     .early_init = soc15_common_early_init,
1425     .late_init = soc15_common_late_init,
1426     .sw_init = soc15_common_sw_init,
1427     .sw_fini = soc15_common_sw_fini,
1428     .hw_init = soc15_common_hw_init,
1429     .hw_fini = soc15_common_hw_fini,
1430     .suspend = soc15_common_suspend,
1431     .resume = soc15_common_resume,
1432     .is_idle = soc15_common_is_idle,
1433     .wait_for_idle = soc15_common_wait_for_idle,
1434     .soft_reset = soc15_common_soft_reset,
1435     .set_clockgating_state = soc15_common_set_clockgating_state,
1436     .set_powergating_state = soc15_common_set_powergating_state,
1437     .get_clockgating_state= soc15_common_get_clockgating_state,
1438 };
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