amd/amdgpu/smuio_v13_0.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "smuio_v13_0.h"
0025 #include "smuio/smuio_13_0_2_offset.h"
0026 #include "smuio/smuio_13_0_2_sh_mask.h"
0027
0028 #define SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK    0x00000001L
0029
0030 static u32 smuio_v13_0_get_rom_index_offset(struct amdgpu_device *adev)
0031 {
0032     return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
0033 }
0034
0035 static u32 smuio_v13_0_get_rom_data_offset(struct amdgpu_device *adev)
0036 {
0037     return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
0038 }
0039
0040 static void smuio_v13_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
0041 {
0042     u32 def, data;
0043
0044     /* enable/disable ROM CG is not supported on APU */
0045     if (adev->flags & AMD_IS_APU)
0046         return;
0047
0048     def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);
0049
0050     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
0051         data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
0052             CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
0053     else
0054         data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
0055             CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
0056
0057     if (def != data)
0058         WREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0, data);
0059 }
0060
0061 static void smuio_v13_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
0062 {
0063     u32 data;
0064
0065     /* CGTT_ROM_CLK_CTRL0 is not available for APU */
0066     if (adev->flags & AMD_IS_APU)
0067         return;
0068
0069     data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);
0070     if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
0071         *flags |= AMD_CG_SUPPORT_ROM_MGCG;
0072 }
0073
0074 /**
0075  * smuio_v13_0_get_die_id - query die id from FCH.
0076  *
0077  * @adev: amdgpu device pointer
0078  *
0079  * Returns die id
0080  */
0081 static u32 smuio_v13_0_get_die_id(struct amdgpu_device *adev)
0082 {
0083     u32 data, die_id;
0084
0085     data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
0086     die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID);
0087
0088     return die_id;
0089 }
0090
0091 /**
0092  * smuio_v13_0_get_socket_id - query socket id from FCH
0093  *
0094  * @adev: amdgpu device pointer
0095  *
0096  * Returns socket id
0097  */
0098 static u32 smuio_v13_0_get_socket_id(struct amdgpu_device *adev)
0099 {
0100     u32 data, socket_id;
0101
0102     data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
0103     socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID);
0104
0105     return socket_id;
0106 }
0107
0108 /**
0109  * smuio_v13_0_is_host_gpu_xgmi_supported - detect xgmi interface between cpu and gpu/s.
0110  *
0111  * @adev: amdgpu device pointer
0112  *
0113  * Returns true on success or false otherwise.
0114  */
0115 static bool smuio_v13_0_is_host_gpu_xgmi_supported(struct amdgpu_device *adev)
0116 {
0117     u32 data;
0118
0119     data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
0120     data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID);
0121     /* data[4:0]
0122      * bit 0 == 0 host-gpu interface is PCIE
0123      * bit 0 == 1 host-gpu interface is Alternate Protocal
0124      * for AMD, this is XGMI
0125      */
0126     data &= SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK;
0127
0128     return data ? true : false;
0129 }
0130
0131 const struct amdgpu_smuio_funcs smuio_v13_0_funcs = {
0132     .get_rom_index_offset = smuio_v13_0_get_rom_index_offset,
0133     .get_rom_data_offset = smuio_v13_0_get_rom_data_offset,
0134     .get_die_id = smuio_v13_0_get_die_id,
0135     .get_socket_id = smuio_v13_0_get_socket_id,
0136     .is_host_gpu_xgmi_supported = smuio_v13_0_is_host_gpu_xgmi_supported,
0137     .update_rom_clock_gating = smuio_v13_0_update_rom_clock_gating,
0138     .get_clock_gating_state = smuio_v13_0_get_clock_gating_state,
0139 };