amd/amdgpu/smuio_v11_0.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "smuio_v11_0.h"
0025 #include "smuio/smuio_11_0_0_offset.h"
0026 #include "smuio/smuio_11_0_0_sh_mask.h"
0027
0028 static u32 smuio_v11_0_get_rom_index_offset(struct amdgpu_device *adev)
0029 {
0030     return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
0031 }
0032
0033 static u32 smuio_v11_0_get_rom_data_offset(struct amdgpu_device *adev)
0034 {
0035     return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
0036 }
0037
0038 static void smuio_v11_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
0039 {
0040     u32 def, data;
0041
0042     /* enable/disable ROM CG is not supported on APU */
0043     if (adev->flags & AMD_IS_APU)
0044         return;
0045
0046     if (!(adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
0047         return;
0048
0049     def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
0050
0051     if (enable)
0052         data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
0053             CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
0054     else
0055         data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
0056             CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
0057
0058     if (def != data)
0059         WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);
0060 }
0061
0062 static void smuio_v11_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
0063 {
0064     u32 data;
0065
0066     /* CGTT_ROM_CLK_CTRL0 is not available for APU */
0067     if (adev->flags & AMD_IS_APU)
0068         return;
0069
0070     data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
0071     if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
0072         *flags |= AMD_CG_SUPPORT_ROM_MGCG;
0073 }
0074
0075 const struct amdgpu_smuio_funcs smuio_v11_0_funcs = {
0076     .get_rom_index_offset = smuio_v11_0_get_rom_index_offset,
0077     .get_rom_data_offset = smuio_v11_0_get_rom_data_offset,
0078     .update_rom_clock_gating = smuio_v11_0_update_rom_clock_gating,
0079     .get_clock_gating_state = smuio_v11_0_get_clock_gating_state,
0080 };