amd/amdgpu/smu_v11_0_i2c.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "smuio/smuio_11_0_0_offset.h"
0025 #include "smuio/smuio_11_0_0_sh_mask.h"
0026
0027 #include "smu_v11_0_i2c.h"
0028 #include "amdgpu.h"
0029 #include "amdgpu_dpm.h"
0030 #include "soc15_common.h"
0031 #include <drm/drm_fixed.h>
0032 #include <drm/drm_drv.h>
0033 #include "amdgpu_amdkfd.h"
0034 #include <linux/i2c.h>
0035 #include <linux/pci.h>
0036
0037 /* error codes */
0038 #define I2C_OK                0
0039 #define I2C_NAK_7B_ADDR_NOACK 1
0040 #define I2C_NAK_TXDATA_NOACK  2
0041 #define I2C_TIMEOUT           4
0042 #define I2C_SW_TIMEOUT        8
0043 #define I2C_ABORT             0x10
0044
0045 #define I2C_X_RESTART         BIT(31)
0046
0047 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
0048 {
0049     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0050     struct amdgpu_device *adev = smu_i2c->adev;
0051     uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
0052
0053     reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
0054     WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
0055 }
0056
0057 /* The T_I2C_POLL_US is defined as follows:
0058  *
0059  * "Define a timer interval (t_i2c_poll) equal to 10 times the
0060  *  signalling period for the highest I2C transfer speed used in the
0061  *  system and supported by DW_apb_i2c. For instance, if the highest
0062  *  I2C data transfer mode is 400 kb/s, then t_i2c_poll is 25 us."  --
0063  * DesignWare DW_apb_i2c Databook, Version 1.21a, section 3.8.3.1,
0064  * page 56, with grammar and syntax corrections.
0065  *
0066  * Vcc for our device is at 1.8V which puts it at 400 kHz,
0067  * see Atmel AT24CM02 datasheet, section 8.3 DC Characteristics table, page 14.
0068  *
0069  * The procedure to disable the IP block is described in section
0070  * 3.8.3 Disabling DW_apb_i2c on page 56.
0071  */
0072 #define I2C_SPEED_MODE_FAST     2
0073 #define T_I2C_POLL_US           25
0074 #define I2C_MAX_T_POLL_COUNT    1000
0075
0076 static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
0077 {
0078     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0079     struct amdgpu_device *adev = smu_i2c->adev;
0080
0081     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
0082
0083     if (!enable) {
0084         int ii;
0085
0086         for (ii = I2C_MAX_T_POLL_COUNT; ii > 0; ii--) {
0087             u32 en_stat = RREG32_SOC15(SMUIO,
0088                            0,
0089                            mmCKSVII2C_IC_ENABLE_STATUS);
0090             if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN))
0091                 udelay(T_I2C_POLL_US);
0092             else
0093                 return I2C_OK;
0094         }
0095
0096         return I2C_ABORT;
0097     }
0098
0099     return I2C_OK;
0100 }
0101
0102 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
0103 {
0104     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0105     struct amdgpu_device *adev = smu_i2c->adev;
0106     /* do */
0107     {
0108         RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
0109
0110     } /* while (reg_CKSVII2C_ic_clr_intr == 0) */
0111 }
0112
0113 static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
0114 {
0115     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0116     struct amdgpu_device *adev = smu_i2c->adev;
0117     uint32_t reg = 0;
0118
0119     reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
0120     reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
0121     reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
0122     reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
0123     /* The values of IC_MAX_SPEED_MODE are,
0124      * 1: standard mode, 0 - 100 Kb/s,
0125      * 2: fast mode, <= 400 Kb/s, or fast mode plus, <= 1000 Kb/s,
0126      * 3: high speed mode, <= 3.4 Mb/s.
0127      */
0128     reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE,
0129                 I2C_SPEED_MODE_FAST);
0130     reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
0131
0132     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
0133 }
0134
0135 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
0136 {
0137     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0138     struct amdgpu_device *adev = smu_i2c->adev;
0139
0140     /*
0141      * Standard mode speed, These values are taken from SMUIO MAS,
0142      * but are different from what is given is
0143      * Synopsys spec. The values here are based on assumption
0144      * that refclock is 100MHz
0145      *
0146      * Configuration for standard mode; Speed = 100kbps
0147      * Scale linearly, for now only support standard speed clock
0148      * This will work only with 100M ref clock
0149      *
0150      * TBD:Change the calculation to take into account ref clock values also.
0151      */
0152
0153     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
0154     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
0155     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
0156     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
0157 }
0158
0159 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16 address)
0160 {
0161     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0162     struct amdgpu_device *adev = smu_i2c->adev;
0163
0164     /* The IC_TAR::IC_TAR field is 10-bits wide.
0165      * It takes a 7-bit or 10-bit addresses as an address,
0166      * i.e. no read/write bit--no wire format, just the address.
0167      */
0168     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, address & 0x3FF);
0169 }
0170
0171 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
0172 {
0173     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0174     struct amdgpu_device *adev = smu_i2c->adev;
0175     uint32_t ret = I2C_OK;
0176     uint32_t reg, reg_c_tx_abrt_source;
0177
0178     /*Check if transmission is completed */
0179     unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
0180
0181     do {
0182         if (time_after(jiffies, timeout_counter)) {
0183             ret |= I2C_SW_TIMEOUT;
0184             break;
0185         }
0186
0187         reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
0188
0189     } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
0190
0191     if (ret != I2C_OK)
0192         return ret;
0193
0194     /* This only checks if NAK is received and transaction got aborted */
0195     reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
0196
0197     if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
0198         reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
0199         DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
0200
0201         /* Check for stop due to NACK */
0202         if (REG_GET_FIELD(reg_c_tx_abrt_source,
0203                   CKSVII2C_IC_TX_ABRT_SOURCE,
0204                   ABRT_TXDATA_NOACK) == 1) {
0205
0206             ret |= I2C_NAK_TXDATA_NOACK;
0207
0208         } else if (REG_GET_FIELD(reg_c_tx_abrt_source,
0209                      CKSVII2C_IC_TX_ABRT_SOURCE,
0210                      ABRT_7B_ADDR_NOACK) == 1) {
0211
0212             ret |= I2C_NAK_7B_ADDR_NOACK;
0213         } else {
0214             ret |= I2C_ABORT;
0215         }
0216
0217         smu_v11_0_i2c_clear_status(control);
0218     }
0219
0220     return ret;
0221 }
0222
0223 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
0224 {
0225     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0226     struct amdgpu_device *adev = smu_i2c->adev;
0227     uint32_t ret = I2C_OK;
0228     uint32_t reg_ic_status, reg_c_tx_abrt_source;
0229
0230     reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
0231
0232     /* If slave is not present */
0233     if (REG_GET_FIELD(reg_c_tx_abrt_source,
0234               CKSVII2C_IC_TX_ABRT_SOURCE,
0235               ABRT_7B_ADDR_NOACK) == 1) {
0236         ret |= I2C_NAK_7B_ADDR_NOACK;
0237
0238         smu_v11_0_i2c_clear_status(control);
0239     } else {  /* wait till some data is there in RXFIFO */
0240         /* Poll for some byte in RXFIFO */
0241         unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
0242
0243         do {
0244             if (time_after(jiffies, timeout_counter)) {
0245                 ret |= I2C_SW_TIMEOUT;
0246                 break;
0247             }
0248
0249             reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
0250
0251         } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
0252     }
0253
0254     return ret;
0255 }
0256
0257 /**
0258  * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
0259  *
0260  * @control: I2C adapter reference
0261  * @address: The I2C address of the slave device.
0262  * @data: The data to transmit over the bus.
0263  * @numbytes: The amount of data to transmit.
0264  * @i2c_flag: Flags for transmission
0265  *
0266  * Returns 0 on success or error.
0267  */
0268 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
0269                        u16 address, u8 *data,
0270                        u32 numbytes, u32 i2c_flag)
0271 {
0272     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0273     struct amdgpu_device *adev = smu_i2c->adev;
0274     u32 bytes_sent, reg, ret = I2C_OK;
0275     unsigned long  timeout_counter;
0276
0277     bytes_sent = 0;
0278
0279     DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
0280              address, numbytes);
0281
0282     if (drm_debug_enabled(DRM_UT_DRIVER)) {
0283         print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
0284                    16, 1, data, numbytes, false);
0285     }
0286
0287     /* Set the I2C slave address */
0288     smu_v11_0_i2c_set_address(control, address);
0289     /* Enable I2C */
0290     smu_v11_0_i2c_enable(control, true);
0291
0292     /* Clear status bits */
0293     smu_v11_0_i2c_clear_status(control);
0294
0295     timeout_counter = jiffies + msecs_to_jiffies(20);
0296
0297     while (numbytes > 0) {
0298         reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
0299         if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
0300             /*
0301              * We waited for too long for the transmission
0302              * FIFO to become not-full.  Exit the loop
0303              * with error.
0304              */
0305             if (time_after(jiffies, timeout_counter)) {
0306                 ret |= I2C_SW_TIMEOUT;
0307                 goto Err;
0308             }
0309         } else {
0310             reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT,
0311                         data[bytes_sent]);
0312
0313             /* Final message, final byte, must generate a
0314              * STOP to release the bus, i.e. don't hold
0315              * SCL low.
0316              */
0317             if (numbytes == 1 && i2c_flag & I2C_M_STOP)
0318                 reg = REG_SET_FIELD(reg,
0319                             CKSVII2C_IC_DATA_CMD,
0320                             STOP, 1);
0321
0322             if (bytes_sent == 0 && i2c_flag & I2C_X_RESTART)
0323                 reg = REG_SET_FIELD(reg,
0324                             CKSVII2C_IC_DATA_CMD,
0325                             RESTART, 1);
0326
0327             /* Write */
0328             reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
0329             WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
0330
0331             /* Record that the bytes were transmitted */
0332             bytes_sent++;
0333             numbytes--;
0334         }
0335     }
0336
0337     ret = smu_v11_0_i2c_poll_tx_status(control);
0338 Err:
0339     /* Any error, no point in proceeding */
0340     if (ret != I2C_OK) {
0341         if (ret & I2C_SW_TIMEOUT)
0342             DRM_ERROR("TIMEOUT ERROR !!!");
0343
0344         if (ret & I2C_NAK_7B_ADDR_NOACK)
0345             DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
0346
0347
0348         if (ret & I2C_NAK_TXDATA_NOACK)
0349             DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
0350     }
0351
0352     return ret;
0353 }
0354
0355
0356 /**
0357  * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
0358  *
0359  * @control: I2C adapter reference
0360  * @address: The I2C address of the slave device.
0361  * @data: Placeholder to store received data.
0362  * @numbytes: The amount of data to transmit.
0363  * @i2c_flag: Flags for transmission
0364  *
0365  * Returns 0 on success or error.
0366  */
0367 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
0368                       u16 address, u8 *data,
0369                       u32 numbytes, u32 i2c_flag)
0370 {
0371     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0372     struct amdgpu_device *adev = smu_i2c->adev;
0373     uint32_t bytes_received, ret = I2C_OK;
0374
0375     bytes_received = 0;
0376
0377     /* Set the I2C slave address */
0378     smu_v11_0_i2c_set_address(control, address);
0379
0380     /* Enable I2C */
0381     smu_v11_0_i2c_enable(control, true);
0382
0383     while (numbytes > 0) {
0384         uint32_t reg = 0;
0385
0386         smu_v11_0_i2c_clear_status(control);
0387
0388         /* Prepare transaction */
0389         reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
0390         /* Read */
0391         reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
0392
0393         /* Final message, final byte, must generate a STOP
0394          * to release the bus, i.e. don't hold SCL low.
0395          */
0396         if (numbytes == 1 && i2c_flag & I2C_M_STOP)
0397             reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
0398                         STOP, 1);
0399
0400         if (bytes_received == 0 && i2c_flag & I2C_X_RESTART)
0401             reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
0402                         RESTART, 1);
0403
0404         WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
0405
0406         ret = smu_v11_0_i2c_poll_rx_status(control);
0407
0408         /* Any error, no point in proceeding */
0409         if (ret != I2C_OK) {
0410             if (ret & I2C_SW_TIMEOUT)
0411                 DRM_ERROR("TIMEOUT ERROR !!!");
0412
0413             if (ret & I2C_NAK_7B_ADDR_NOACK)
0414                 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
0415
0416             if (ret & I2C_NAK_TXDATA_NOACK)
0417                 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
0418
0419             break;
0420         }
0421
0422         reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
0423         data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
0424
0425         /* Record that the bytes were received */
0426         bytes_received++;
0427         numbytes--;
0428     }
0429
0430     DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
0431           (uint16_t)address, bytes_received);
0432
0433     if (drm_debug_enabled(DRM_UT_DRIVER)) {
0434         print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
0435                    16, 1, data, bytes_received, false);
0436     }
0437
0438     return ret;
0439 }
0440
0441 static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
0442 {
0443     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0444     struct amdgpu_device *adev = smu_i2c->adev;
0445     uint32_t reg = 0;
0446
0447     /* Enable I2C engine; */
0448     reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
0449     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
0450
0451     /* Abort previous transaction */
0452     reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
0453     WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
0454
0455     DRM_DEBUG_DRIVER("I2C_Abort() Done.");
0456 }
0457
0458 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
0459 {
0460     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0461     struct amdgpu_device *adev = smu_i2c->adev;
0462
0463     const uint32_t IDLE_TIMEOUT = 1024;
0464     uint32_t timeout_count = 0;
0465     uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
0466
0467     reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
0468     reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
0469
0470     if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
0471         (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
0472         /*
0473          * Nobody is using I2C engine, but engine remains active because
0474          * someone missed to send STOP
0475          */
0476         smu_v11_0_i2c_abort(control);
0477     } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
0478         /* Nobody is using I2C engine */
0479         return true;
0480     }
0481
0482     /* Keep reading activity bit until it's cleared */
0483     do {
0484         reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
0485
0486         if (REG_GET_FIELD(reg_ic_clr_activity,
0487             CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
0488             return true;
0489
0490         ++timeout_count;
0491
0492     } while (timeout_count < IDLE_TIMEOUT);
0493
0494     return false;
0495 }
0496
0497 static void smu_v11_0_i2c_init(struct i2c_adapter *control)
0498 {
0499     int res;
0500
0501     /* Disable clock gating */
0502     smu_v11_0_i2c_set_clock_gating(control, false);
0503
0504     if (!smu_v11_0_i2c_activity_done(control))
0505         DRM_WARN("I2C busy !");
0506
0507     /* Disable I2C */
0508     res = smu_v11_0_i2c_enable(control, false);
0509     if (res != I2C_OK)
0510         smu_v11_0_i2c_abort(control);
0511
0512     /* Configure I2C to operate as master and in standard mode */
0513     smu_v11_0_i2c_configure(control);
0514
0515     /* Initialize the clock to 50 kHz default */
0516     smu_v11_0_i2c_set_clock(control);
0517
0518 }
0519
0520 static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
0521 {
0522     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0523     struct amdgpu_device *adev = smu_i2c->adev;
0524     u32 status, enable, en_stat;
0525     int res;
0526
0527     res = smu_v11_0_i2c_enable(control, false);
0528     if (res != I2C_OK) {
0529         status  = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
0530         enable  = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
0531         en_stat = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
0532
0533         /* Nobody is using the I2C engine, yet it remains
0534          * active, possibly because someone missed to send
0535          * STOP.
0536          */
0537         DRM_DEBUG_DRIVER("Aborting from fini: status:0x%08x "
0538                  "enable:0x%08x enable_stat:0x%08x",
0539                  status, enable, en_stat);
0540         smu_v11_0_i2c_abort(control);
0541     }
0542
0543     /* Restore clock gating */
0544
0545     /*
0546      * TODO Reenabling clock gating seems to break subsequent SMU operation
0547      *      on the I2C bus. My guess is that SMU doesn't disable clock gating like
0548      *      we do here before working with the bus. So for now just don't restore
0549      *      it but later work with SMU to see if they have this issue and can
0550      *      update their code appropriately
0551      */
0552     /* smu_v11_0_i2c_set_clock_gating(control, true); */
0553
0554 }
0555
0556 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
0557 {
0558     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0559     struct amdgpu_device *adev = smu_i2c->adev;
0560
0561     /* Send  PPSMC_MSG_RequestI2CBus */
0562     if (!amdgpu_dpm_smu_i2c_bus_access(adev, true))
0563         return true;
0564
0565     return false;
0566 }
0567
0568 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
0569 {
0570     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
0571     struct amdgpu_device *adev = smu_i2c->adev;
0572
0573     /* Send  PPSMC_MSG_ReleaseI2CBus */
0574     if (!amdgpu_dpm_smu_i2c_bus_access(adev, false))
0575         return true;
0576
0577     return false;
0578 }
0579
0580 /***************************** I2C GLUE ****************************/
0581
0582 static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control,
0583                     struct i2c_msg *msg, uint32_t i2c_flag)
0584 {
0585     uint32_t  ret;
0586
0587     ret = smu_v11_0_i2c_receive(control, msg->addr, msg->buf, msg->len, i2c_flag);
0588
0589     if (ret != I2C_OK)
0590         DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
0591
0592     return ret;
0593 }
0594
0595 static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control,
0596                     struct i2c_msg *msg, uint32_t i2c_flag)
0597 {
0598     uint32_t  ret;
0599
0600     ret = smu_v11_0_i2c_transmit(control, msg->addr, msg->buf, msg->len, i2c_flag);
0601
0602     if (ret != I2C_OK)
0603         DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
0604
0605     return ret;
0606
0607 }
0608
0609 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
0610 {
0611     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c);
0612     struct amdgpu_device *adev = smu_i2c->adev;
0613
0614     mutex_lock(&smu_i2c->mutex);
0615     if (!smu_v11_0_i2c_bus_lock(i2c))
0616         DRM_ERROR("Failed to lock the bus from SMU");
0617     else
0618         adev->pm.bus_locked = true;
0619 }
0620
0621 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
0622 {
0623     WARN_ONCE(1, "This operation not supposed to run in atomic context!");
0624     return false;
0625 }
0626
0627 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
0628 {
0629     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c);
0630     struct amdgpu_device *adev = smu_i2c->adev;
0631
0632     if (!smu_v11_0_i2c_bus_unlock(i2c))
0633         DRM_ERROR("Failed to unlock the bus from SMU");
0634     else
0635         adev->pm.bus_locked = false;
0636     mutex_unlock(&smu_i2c->mutex);
0637 }
0638
0639 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
0640     .lock_bus = lock_bus,
0641     .trylock_bus = trylock_bus,
0642     .unlock_bus = unlock_bus,
0643 };
0644
0645 static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap,
0646                   struct i2c_msg *msg, int num)
0647 {
0648     int i, ret;
0649     u16 addr, dir;
0650
0651     smu_v11_0_i2c_init(i2c_adap);
0652
0653     /* From the client's point of view, this sequence of
0654      * messages-- the array i2c_msg *msg, is a single transaction
0655      * on the bus, starting with START and ending with STOP.
0656      *
0657      * The client is welcome to send any sequence of messages in
0658      * this array, as processing under this function here is
0659      * striving to be agnostic.
0660      *
0661      * Record the first address and direction we see. If either
0662      * changes for a subsequent message, generate ReSTART. The
0663      * DW_apb_i2c databook, v1.21a, specifies that ReSTART is
0664      * generated when the direction changes, with the default IP
0665      * block parameter settings, but it doesn't specify if ReSTART
0666      * is generated when the address changes (possibly...). We
0667      * don't rely on the default IP block parameter settings as
0668      * the block is shared and they may change.
0669      */
0670     if (num > 0) {
0671         addr = msg[0].addr;
0672         dir  = msg[0].flags & I2C_M_RD;
0673     }
0674
0675     for (i = 0; i < num; i++) {
0676         u32 i2c_flag = 0;
0677
0678         if (msg[i].addr != addr || (msg[i].flags ^ dir) & I2C_M_RD) {
0679             addr = msg[i].addr;
0680             dir  = msg[i].flags & I2C_M_RD;
0681             i2c_flag |= I2C_X_RESTART;
0682         }
0683
0684         if (i == num - 1) {
0685             /* Set the STOP bit on the last message, so
0686              * that the IP block generates a STOP after
0687              * the last byte of the message.
0688              */
0689             i2c_flag |= I2C_M_STOP;
0690         }
0691
0692         if (msg[i].flags & I2C_M_RD)
0693             ret = smu_v11_0_i2c_read_data(i2c_adap,
0694                               msg + i,
0695                               i2c_flag);
0696         else
0697             ret = smu_v11_0_i2c_write_data(i2c_adap,
0698                                msg + i,
0699                                i2c_flag);
0700
0701         if (ret != I2C_OK) {
0702             num = -EIO;
0703             break;
0704         }
0705     }
0706
0707     smu_v11_0_i2c_fini(i2c_adap);
0708     return num;
0709 }
0710
0711 static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap)
0712 {
0713     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0714 }
0715
0716 static const struct i2c_algorithm smu_v11_0_i2c_algo = {
0717     .master_xfer = smu_v11_0_i2c_xfer,
0718     .functionality = smu_v11_0_i2c_func,
0719 };
0720
0721 static const struct i2c_adapter_quirks smu_v11_0_i2c_control_quirks = {
0722     .flags = I2C_AQ_NO_ZERO_LEN,
0723 };
0724
0725 int smu_v11_0_i2c_control_init(struct amdgpu_device *adev)
0726 {
0727     struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
0728     struct i2c_adapter *control = &smu_i2c->adapter;
0729     int res;
0730
0731     smu_i2c->adev = adev;
0732     smu_i2c->port = 0;
0733     mutex_init(&smu_i2c->mutex);
0734     control->owner = THIS_MODULE;
0735     control->class = I2C_CLASS_HWMON;
0736     control->dev.parent = &adev->pdev->dev;
0737     control->algo = &smu_v11_0_i2c_algo;
0738     snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
0739     control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
0740     control->quirks = &smu_v11_0_i2c_control_quirks;
0741     i2c_set_adapdata(control, smu_i2c);
0742
0743     adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
0744     adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
0745
0746     res = i2c_add_adapter(control);
0747     if (res)
0748         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
0749
0750     return res;
0751 }
0752
0753 void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev)
0754 {
0755     struct i2c_adapter *control = adev->pm.ras_eeprom_i2c_bus;
0756
0757     i2c_del_adapter(control);
0758     adev->pm.ras_eeprom_i2c_bus = NULL;
0759     adev->pm.fru_eeprom_i2c_bus = NULL;
0760 }
0761
0762 /*
0763  * Keep this for future unit test if bugs arise
0764  */
0765 #if 0
0766 #define I2C_TARGET_ADDR 0xA0
0767
0768 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
0769 {
0770
0771     uint32_t ret = I2C_OK;
0772     uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
0773
0774
0775     DRM_INFO("Begin");
0776
0777     if (!smu_v11_0_i2c_bus_lock(control)) {
0778         DRM_ERROR("Failed to lock the bus!.");
0779         return false;
0780     }
0781
0782     smu_v11_0_i2c_init(control);
0783
0784     /* Write 0xde to address 0x0000 on the EEPROM */
0785     ret = smu_v11_0_i2c_write_data(control, I2C_TARGET_ADDR, data, 6);
0786
0787     ret = smu_v11_0_i2c_read_data(control, I2C_TARGET_ADDR, data, 6);
0788
0789     smu_v11_0_i2c_fini(control);
0790
0791     smu_v11_0_i2c_bus_unlock(control);
0792
0793
0794     DRM_INFO("End");
0795     return true;
0796 }
0797 #endif