amd/amdgpu/si_ih.c

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include <linux/pci.h>
0025
0026 #include "amdgpu.h"
0027 #include "amdgpu_ih.h"
0028 #include "sid.h"
0029 #include "si_ih.h"
0030 #include "oss/oss_1_0_d.h"
0031 #include "oss/oss_1_0_sh_mask.h"
0032
0033 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
0034
0035 static void si_ih_enable_interrupts(struct amdgpu_device *adev)
0036 {
0037     u32 ih_cntl = RREG32(IH_CNTL);
0038     u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
0039
0040     ih_cntl |= ENABLE_INTR;
0041     ih_rb_cntl |= IH_RB_ENABLE;
0042     WREG32(IH_CNTL, ih_cntl);
0043     WREG32(IH_RB_CNTL, ih_rb_cntl);
0044     adev->irq.ih.enabled = true;
0045 }
0046
0047 static void si_ih_disable_interrupts(struct amdgpu_device *adev)
0048 {
0049     u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
0050     u32 ih_cntl = RREG32(IH_CNTL);
0051
0052     ih_rb_cntl &= ~IH_RB_ENABLE;
0053     ih_cntl &= ~ENABLE_INTR;
0054     WREG32(IH_RB_CNTL, ih_rb_cntl);
0055     WREG32(IH_CNTL, ih_cntl);
0056     WREG32(IH_RB_RPTR, 0);
0057     WREG32(IH_RB_WPTR, 0);
0058     adev->irq.ih.enabled = false;
0059     adev->irq.ih.rptr = 0;
0060 }
0061
0062 static int si_ih_irq_init(struct amdgpu_device *adev)
0063 {
0064     struct amdgpu_ih_ring *ih = &adev->irq.ih;
0065     int rb_bufsz;
0066     u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
0067
0068     si_ih_disable_interrupts(adev);
0069     /* set dummy read address to dummy page address */
0070     WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
0071     interrupt_cntl = RREG32(INTERRUPT_CNTL);
0072     interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
0073     interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
0074     WREG32(INTERRUPT_CNTL, interrupt_cntl);
0075
0076     WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
0077     rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
0078
0079     ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE |
0080              IH_WPTR_OVERFLOW_CLEAR |
0081              (rb_bufsz << 1) |
0082              IH_WPTR_WRITEBACK_ENABLE;
0083
0084     WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
0085     WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
0086     WREG32(IH_RB_CNTL, ih_rb_cntl);
0087     WREG32(IH_RB_RPTR, 0);
0088     WREG32(IH_RB_WPTR, 0);
0089
0090     ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
0091     if (adev->irq.msi_enabled)
0092         ih_cntl |= RPTR_REARM;
0093     WREG32(IH_CNTL, ih_cntl);
0094
0095     pci_set_master(adev->pdev);
0096     si_ih_enable_interrupts(adev);
0097
0098     return 0;
0099 }
0100
0101 static void si_ih_irq_disable(struct amdgpu_device *adev)
0102 {
0103     si_ih_disable_interrupts(adev);
0104     mdelay(1);
0105 }
0106
0107 static u32 si_ih_get_wptr(struct amdgpu_device *adev,
0108               struct amdgpu_ih_ring *ih)
0109 {
0110     u32 wptr, tmp;
0111
0112     wptr = le32_to_cpu(*ih->wptr_cpu);
0113
0114     if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
0115         wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
0116         dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
0117             wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
0118         ih->rptr = (wptr + 16) & ih->ptr_mask;
0119         tmp = RREG32(IH_RB_CNTL);
0120         tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
0121         WREG32(IH_RB_CNTL, tmp);
0122     }
0123     return (wptr & ih->ptr_mask);
0124 }
0125
0126 static void si_ih_decode_iv(struct amdgpu_device *adev,
0127                 struct amdgpu_ih_ring *ih,
0128                 struct amdgpu_iv_entry *entry)
0129 {
0130     u32 ring_index = ih->rptr >> 2;
0131     uint32_t dw[4];
0132
0133     dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
0134     dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
0135     dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
0136     dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
0137
0138     entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
0139     entry->src_id = dw[0] & 0xff;
0140     entry->src_data[0] = dw[1] & 0xfffffff;
0141     entry->ring_id = dw[2] & 0xff;
0142     entry->vmid = (dw[2] >> 8) & 0xff;
0143
0144     ih->rptr += 16;
0145 }
0146
0147 static void si_ih_set_rptr(struct amdgpu_device *adev,
0148                struct amdgpu_ih_ring *ih)
0149 {
0150     WREG32(IH_RB_RPTR, ih->rptr);
0151 }
0152
0153 static int si_ih_early_init(void *handle)
0154 {
0155     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0156
0157     si_ih_set_interrupt_funcs(adev);
0158
0159     return 0;
0160 }
0161
0162 static int si_ih_sw_init(void *handle)
0163 {
0164     int r;
0165     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0166
0167     r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
0168     if (r)
0169         return r;
0170
0171     return amdgpu_irq_init(adev);
0172 }
0173
0174 static int si_ih_sw_fini(void *handle)
0175 {
0176     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0177
0178     amdgpu_irq_fini_sw(adev);
0179
0180     return 0;
0181 }
0182
0183 static int si_ih_hw_init(void *handle)
0184 {
0185     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0186
0187     return si_ih_irq_init(adev);
0188 }
0189
0190 static int si_ih_hw_fini(void *handle)
0191 {
0192     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0193
0194     si_ih_irq_disable(adev);
0195
0196     return 0;
0197 }
0198
0199 static int si_ih_suspend(void *handle)
0200 {
0201     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0202
0203     return si_ih_hw_fini(adev);
0204 }
0205
0206 static int si_ih_resume(void *handle)
0207 {
0208     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0209
0210     return si_ih_hw_init(adev);
0211 }
0212
0213 static bool si_ih_is_idle(void *handle)
0214 {
0215     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0216     u32 tmp = RREG32(SRBM_STATUS);
0217
0218     if (tmp & SRBM_STATUS__IH_BUSY_MASK)
0219         return false;
0220
0221     return true;
0222 }
0223
0224 static int si_ih_wait_for_idle(void *handle)
0225 {
0226     unsigned i;
0227     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0228
0229     for (i = 0; i < adev->usec_timeout; i++) {
0230         if (si_ih_is_idle(handle))
0231             return 0;
0232         udelay(1);
0233     }
0234     return -ETIMEDOUT;
0235 }
0236
0237 static int si_ih_soft_reset(void *handle)
0238 {
0239     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0240
0241     u32 srbm_soft_reset = 0;
0242     u32 tmp = RREG32(SRBM_STATUS);
0243
0244     if (tmp & SRBM_STATUS__IH_BUSY_MASK)
0245         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
0246
0247     if (srbm_soft_reset) {
0248         tmp = RREG32(SRBM_SOFT_RESET);
0249         tmp |= srbm_soft_reset;
0250         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
0251         WREG32(SRBM_SOFT_RESET, tmp);
0252         tmp = RREG32(SRBM_SOFT_RESET);
0253
0254         udelay(50);
0255
0256         tmp &= ~srbm_soft_reset;
0257         WREG32(SRBM_SOFT_RESET, tmp);
0258         tmp = RREG32(SRBM_SOFT_RESET);
0259
0260         udelay(50);
0261     }
0262
0263     return 0;
0264 }
0265
0266 static int si_ih_set_clockgating_state(void *handle,
0267                       enum amd_clockgating_state state)
0268 {
0269     return 0;
0270 }
0271
0272 static int si_ih_set_powergating_state(void *handle,
0273                       enum amd_powergating_state state)
0274 {
0275     return 0;
0276 }
0277
0278 static const struct amd_ip_funcs si_ih_ip_funcs = {
0279     .name = "si_ih",
0280     .early_init = si_ih_early_init,
0281     .late_init = NULL,
0282     .sw_init = si_ih_sw_init,
0283     .sw_fini = si_ih_sw_fini,
0284     .hw_init = si_ih_hw_init,
0285     .hw_fini = si_ih_hw_fini,
0286     .suspend = si_ih_suspend,
0287     .resume = si_ih_resume,
0288     .is_idle = si_ih_is_idle,
0289     .wait_for_idle = si_ih_wait_for_idle,
0290     .soft_reset = si_ih_soft_reset,
0291     .set_clockgating_state = si_ih_set_clockgating_state,
0292     .set_powergating_state = si_ih_set_powergating_state,
0293 };
0294
0295 static const struct amdgpu_ih_funcs si_ih_funcs = {
0296     .get_wptr = si_ih_get_wptr,
0297     .decode_iv = si_ih_decode_iv,
0298     .set_rptr = si_ih_set_rptr
0299 };
0300
0301 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
0302 {
0303     adev->irq.ih_funcs = &si_ih_funcs;
0304 }
0305
0306 const struct amdgpu_ip_block_version si_ih_ip_block =
0307 {
0308     .type = AMD_IP_BLOCK_TYPE_IH,
0309     .major = 1,
0310     .minor = 0,
0311     .rev = 0,
0312     .funcs = &si_ih_ip_funcs,
0313 };