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0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <linux/delay.h>
0025 #include <linux/firmware.h>
0026 #include <linux/module.h>
0027 #include <linux/pci.h>
0028 
0029 #include "amdgpu.h"
0030 #include "amdgpu_ucode.h"
0031 #include "amdgpu_trace.h"
0032 
0033 #include "gc/gc_10_3_0_offset.h"
0034 #include "gc/gc_10_3_0_sh_mask.h"
0035 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
0036 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
0037 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
0038 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
0039 
0040 #include "soc15_common.h"
0041 #include "soc15.h"
0042 #include "navi10_sdma_pkt_open.h"
0043 #include "nbio_v2_3.h"
0044 #include "sdma_common.h"
0045 #include "sdma_v5_2.h"
0046 
0047 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
0048 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
0049 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
0050 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
0051 
0052 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
0053 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
0054 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
0055 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
0056 
0057 #define SDMA1_REG_OFFSET 0x600
0058 #define SDMA3_REG_OFFSET 0x400
0059 #define SDMA0_HYP_DEC_REG_START 0x5880
0060 #define SDMA0_HYP_DEC_REG_END 0x5893
0061 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
0062 
0063 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
0064 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
0065 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
0066 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
0067 
0068 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
0069 {
0070     u32 base;
0071 
0072     if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
0073         internal_offset <= SDMA0_HYP_DEC_REG_END) {
0074         base = adev->reg_offset[GC_HWIP][0][1];
0075         if (instance != 0)
0076             internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
0077     } else {
0078         if (instance < 2) {
0079             base = adev->reg_offset[GC_HWIP][0][0];
0080             if (instance == 1)
0081                 internal_offset += SDMA1_REG_OFFSET;
0082         } else {
0083             base = adev->reg_offset[GC_HWIP][0][2];
0084             if (instance == 3)
0085                 internal_offset += SDMA3_REG_OFFSET;
0086         }
0087     }
0088 
0089     return base + internal_offset;
0090 }
0091 
0092 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
0093 {
0094     int err = 0;
0095     const struct sdma_firmware_header_v1_0 *hdr;
0096 
0097     err = amdgpu_ucode_validate(sdma_inst->fw);
0098     if (err)
0099         return err;
0100 
0101     hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
0102     sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
0103     sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
0104 
0105     if (sdma_inst->feature_version >= 20)
0106         sdma_inst->burst_nop = true;
0107 
0108     return 0;
0109 }
0110 
0111 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
0112 {
0113     release_firmware(adev->sdma.instance[0].fw);
0114 
0115     memset((void *)adev->sdma.instance, 0,
0116            sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
0117 }
0118 
0119 /**
0120  * sdma_v5_2_init_microcode - load ucode images from disk
0121  *
0122  * @adev: amdgpu_device pointer
0123  *
0124  * Use the firmware interface to load the ucode images into
0125  * the driver (not loaded into hw).
0126  * Returns 0 on success, error on failure.
0127  */
0128 
0129 // emulation only, won't work on real chip
0130 // navi10 real chip need to use PSP to load firmware
0131 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
0132 {
0133     const char *chip_name;
0134     char fw_name[40];
0135     int err = 0, i;
0136     struct amdgpu_firmware_info *info = NULL;
0137     const struct common_firmware_header *header = NULL;
0138 
0139     DRM_DEBUG("\n");
0140 
0141     switch (adev->ip_versions[SDMA0_HWIP][0]) {
0142     case IP_VERSION(5, 2, 0):
0143         chip_name = "sienna_cichlid_sdma";
0144         break;
0145     case IP_VERSION(5, 2, 2):
0146         chip_name = "navy_flounder_sdma";
0147         break;
0148     case IP_VERSION(5, 2, 1):
0149         chip_name = "vangogh_sdma";
0150         break;
0151     case IP_VERSION(5, 2, 4):
0152         chip_name = "dimgrey_cavefish_sdma";
0153         break;
0154     case IP_VERSION(5, 2, 5):
0155         chip_name = "beige_goby_sdma";
0156         break;
0157     case IP_VERSION(5, 2, 3):
0158         chip_name = "yellow_carp_sdma";
0159         break;
0160     case IP_VERSION(5, 2, 6):
0161         chip_name = "sdma_5_2_6";
0162         break;
0163     case IP_VERSION(5, 2, 7):
0164         chip_name = "sdma_5_2_7";
0165         break;
0166     default:
0167         BUG();
0168     }
0169 
0170     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
0171 
0172     err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
0173     if (err)
0174         goto out;
0175 
0176     err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
0177     if (err)
0178         goto out;
0179 
0180     for (i = 1; i < adev->sdma.num_instances; i++)
0181         memcpy((void *)&adev->sdma.instance[i],
0182                (void *)&adev->sdma.instance[0],
0183                sizeof(struct amdgpu_sdma_instance));
0184 
0185     if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
0186         return 0;
0187 
0188     DRM_DEBUG("psp_load == '%s'\n",
0189           adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
0190 
0191     if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
0192         for (i = 0; i < adev->sdma.num_instances; i++) {
0193             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
0194             info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
0195             info->fw = adev->sdma.instance[i].fw;
0196             header = (const struct common_firmware_header *)info->fw->data;
0197             adev->firmware.fw_size +=
0198                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
0199         }
0200     }
0201 
0202 out:
0203     if (err) {
0204         DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
0205         sdma_v5_2_destroy_inst_ctx(adev);
0206     }
0207     return err;
0208 }
0209 
0210 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
0211 {
0212     unsigned ret;
0213 
0214     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
0215     amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
0216     amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
0217     amdgpu_ring_write(ring, 1);
0218     ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
0219     amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
0220 
0221     return ret;
0222 }
0223 
0224 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
0225                        unsigned offset)
0226 {
0227     unsigned cur;
0228 
0229     BUG_ON(offset > ring->buf_mask);
0230     BUG_ON(ring->ring[offset] != 0x55aa55aa);
0231 
0232     cur = (ring->wptr - 1) & ring->buf_mask;
0233     if (cur > offset)
0234         ring->ring[offset] = cur - offset;
0235     else
0236         ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
0237 }
0238 
0239 /**
0240  * sdma_v5_2_ring_get_rptr - get the current read pointer
0241  *
0242  * @ring: amdgpu ring pointer
0243  *
0244  * Get the current rptr from the hardware (NAVI10+).
0245  */
0246 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
0247 {
0248     u64 *rptr;
0249 
0250     /* XXX check if swapping is necessary on BE */
0251     rptr = (u64 *)ring->rptr_cpu_addr;
0252 
0253     DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
0254     return ((*rptr) >> 2);
0255 }
0256 
0257 /**
0258  * sdma_v5_2_ring_get_wptr - get the current write pointer
0259  *
0260  * @ring: amdgpu ring pointer
0261  *
0262  * Get the current wptr from the hardware (NAVI10+).
0263  */
0264 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
0265 {
0266     struct amdgpu_device *adev = ring->adev;
0267     u64 wptr;
0268 
0269     if (ring->use_doorbell) {
0270         /* XXX check if swapping is necessary on BE */
0271         wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
0272         DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
0273     } else {
0274         wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
0275         wptr = wptr << 32;
0276         wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
0277         DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
0278     }
0279 
0280     return wptr >> 2;
0281 }
0282 
0283 /**
0284  * sdma_v5_2_ring_set_wptr - commit the write pointer
0285  *
0286  * @ring: amdgpu ring pointer
0287  *
0288  * Write the wptr back to the hardware (NAVI10+).
0289  */
0290 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
0291 {
0292     struct amdgpu_device *adev = ring->adev;
0293 
0294     DRM_DEBUG("Setting write pointer\n");
0295     if (ring->use_doorbell) {
0296         DRM_DEBUG("Using doorbell -- "
0297                 "wptr_offs == 0x%08x "
0298                 "lower_32_bits(ring->wptr << 2) == 0x%08x "
0299                 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
0300                 ring->wptr_offs,
0301                 lower_32_bits(ring->wptr << 2),
0302                 upper_32_bits(ring->wptr << 2));
0303         /* XXX check if swapping is necessary on BE */
0304         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
0305                  ring->wptr << 2);
0306         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
0307                 ring->doorbell_index, ring->wptr << 2);
0308         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
0309     } else {
0310         DRM_DEBUG("Not using doorbell -- "
0311                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
0312                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
0313                 ring->me,
0314                 lower_32_bits(ring->wptr << 2),
0315                 ring->me,
0316                 upper_32_bits(ring->wptr << 2));
0317         WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
0318             lower_32_bits(ring->wptr << 2));
0319         WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
0320             upper_32_bits(ring->wptr << 2));
0321     }
0322 }
0323 
0324 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
0325 {
0326     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
0327     int i;
0328 
0329     for (i = 0; i < count; i++)
0330         if (sdma && sdma->burst_nop && (i == 0))
0331             amdgpu_ring_write(ring, ring->funcs->nop |
0332                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
0333         else
0334             amdgpu_ring_write(ring, ring->funcs->nop);
0335 }
0336 
0337 /**
0338  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
0339  *
0340  * @ring: amdgpu ring pointer
0341  * @job: job to retrieve vmid from
0342  * @ib: IB object to schedule
0343  * @flags: unused
0344  *
0345  * Schedule an IB in the DMA ring.
0346  */
0347 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
0348                    struct amdgpu_job *job,
0349                    struct amdgpu_ib *ib,
0350                    uint32_t flags)
0351 {
0352     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
0353     uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
0354 
0355     /* An IB packet must end on a 8 DW boundary--the next dword
0356      * must be on a 8-dword boundary. Our IB packet below is 6
0357      * dwords long, thus add x number of NOPs, such that, in
0358      * modular arithmetic,
0359      * wptr + 6 + x = 8k, k >= 0, which in C is,
0360      * (wptr + 6 + x) % 8 = 0.
0361      * The expression below, is a solution of x.
0362      */
0363     sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
0364 
0365     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
0366               SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
0367     /* base must be 32 byte aligned */
0368     amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
0369     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
0370     amdgpu_ring_write(ring, ib->length_dw);
0371     amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
0372     amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
0373 }
0374 
0375 /**
0376  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
0377  *
0378  * @ring: amdgpu ring pointer
0379  *
0380  * flush the IB by graphics cache rinse.
0381  */
0382 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
0383 {
0384     uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
0385                 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
0386                 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
0387                 SDMA_GCR_GLI_INV(1);
0388 
0389     /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
0390     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
0391     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
0392     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
0393             SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
0394     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
0395             SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
0396     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
0397             SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
0398 }
0399 
0400 /**
0401  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
0402  *
0403  * @ring: amdgpu ring pointer
0404  *
0405  * Emit an hdp flush packet on the requested DMA ring.
0406  */
0407 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
0408 {
0409     struct amdgpu_device *adev = ring->adev;
0410     u32 ref_and_mask = 0;
0411     const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
0412 
0413     ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
0414 
0415     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
0416               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
0417               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
0418     amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
0419     amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
0420     amdgpu_ring_write(ring, ref_and_mask); /* reference */
0421     amdgpu_ring_write(ring, ref_and_mask); /* mask */
0422     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
0423               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
0424 }
0425 
0426 /**
0427  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
0428  *
0429  * @ring: amdgpu ring pointer
0430  * @addr: address
0431  * @seq: sequence number
0432  * @flags: fence related flags
0433  *
0434  * Add a DMA fence packet to the ring to write
0435  * the fence seq number and DMA trap packet to generate
0436  * an interrupt if needed.
0437  */
0438 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0439                       unsigned flags)
0440 {
0441     bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
0442     /* write the fence */
0443     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
0444               SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
0445     /* zero in first two bits */
0446     BUG_ON(addr & 0x3);
0447     amdgpu_ring_write(ring, lower_32_bits(addr));
0448     amdgpu_ring_write(ring, upper_32_bits(addr));
0449     amdgpu_ring_write(ring, lower_32_bits(seq));
0450 
0451     /* optionally write high bits as well */
0452     if (write64bit) {
0453         addr += 4;
0454         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
0455                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
0456         /* zero in first two bits */
0457         BUG_ON(addr & 0x3);
0458         amdgpu_ring_write(ring, lower_32_bits(addr));
0459         amdgpu_ring_write(ring, upper_32_bits(addr));
0460         amdgpu_ring_write(ring, upper_32_bits(seq));
0461     }
0462 
0463     if ((flags & AMDGPU_FENCE_FLAG_INT)) {
0464         uint32_t ctx = ring->is_mes_queue ?
0465             (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
0466         /* generate an interrupt */
0467         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
0468         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
0469     }
0470 }
0471 
0472 
0473 /**
0474  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
0475  *
0476  * @adev: amdgpu_device pointer
0477  *
0478  * Stop the gfx async dma ring buffers.
0479  */
0480 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
0481 {
0482     struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
0483     struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
0484     struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
0485     struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
0486     u32 rb_cntl, ib_cntl;
0487     int i;
0488 
0489     if ((adev->mman.buffer_funcs_ring == sdma0) ||
0490         (adev->mman.buffer_funcs_ring == sdma1) ||
0491         (adev->mman.buffer_funcs_ring == sdma2) ||
0492         (adev->mman.buffer_funcs_ring == sdma3))
0493         amdgpu_ttm_set_buffer_funcs_status(adev, false);
0494 
0495     for (i = 0; i < adev->sdma.num_instances; i++) {
0496         rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
0497         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
0498         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
0499         ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
0500         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
0501         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
0502     }
0503 }
0504 
0505 /**
0506  * sdma_v5_2_rlc_stop - stop the compute async dma engines
0507  *
0508  * @adev: amdgpu_device pointer
0509  *
0510  * Stop the compute async dma queues.
0511  */
0512 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
0513 {
0514     /* XXX todo */
0515 }
0516 
0517 /**
0518  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
0519  *
0520  * @adev: amdgpu_device pointer
0521  * @enable: enable/disable the DMA MEs context switch.
0522  *
0523  * Halt or unhalt the async dma engines context switch.
0524  */
0525 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
0526 {
0527     u32 f32_cntl, phase_quantum = 0;
0528     int i;
0529 
0530     if (amdgpu_sdma_phase_quantum) {
0531         unsigned value = amdgpu_sdma_phase_quantum;
0532         unsigned unit = 0;
0533 
0534         while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0535                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
0536             value = (value + 1) >> 1;
0537             unit++;
0538         }
0539         if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0540                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
0541             value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0542                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
0543             unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0544                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
0545             WARN_ONCE(1,
0546             "clamping sdma_phase_quantum to %uK clock cycles\n",
0547                   value << unit);
0548         }
0549         phase_quantum =
0550             value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
0551             unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
0552     }
0553 
0554     for (i = 0; i < adev->sdma.num_instances; i++) {
0555         if (enable && amdgpu_sdma_phase_quantum) {
0556             WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
0557                    phase_quantum);
0558             WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
0559                    phase_quantum);
0560             WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
0561                    phase_quantum);
0562         }
0563 
0564         if (!amdgpu_sriov_vf(adev)) {
0565             f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
0566             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0567                     AUTO_CTXSW_ENABLE, enable ? 1 : 0);
0568             WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
0569         }
0570     }
0571 
0572 }
0573 
0574 /**
0575  * sdma_v5_2_enable - stop the async dma engines
0576  *
0577  * @adev: amdgpu_device pointer
0578  * @enable: enable/disable the DMA MEs.
0579  *
0580  * Halt or unhalt the async dma engines.
0581  */
0582 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
0583 {
0584     u32 f32_cntl;
0585     int i;
0586 
0587     if (!enable) {
0588         sdma_v5_2_gfx_stop(adev);
0589         sdma_v5_2_rlc_stop(adev);
0590     }
0591 
0592     if (!amdgpu_sriov_vf(adev)) {
0593         for (i = 0; i < adev->sdma.num_instances; i++) {
0594             f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
0595             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
0596             WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
0597         }
0598     }
0599 }
0600 
0601 /**
0602  * sdma_v5_2_gfx_resume - setup and start the async dma engines
0603  *
0604  * @adev: amdgpu_device pointer
0605  *
0606  * Set up the gfx DMA ring buffers and enable them.
0607  * Returns 0 for success, error for failure.
0608  */
0609 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
0610 {
0611     struct amdgpu_ring *ring;
0612     u32 rb_cntl, ib_cntl;
0613     u32 rb_bufsz;
0614     u32 doorbell;
0615     u32 doorbell_offset;
0616     u32 temp;
0617     u32 wptr_poll_cntl;
0618     u64 wptr_gpu_addr;
0619     int i, r;
0620 
0621     for (i = 0; i < adev->sdma.num_instances; i++) {
0622         ring = &adev->sdma.instance[i].ring;
0623 
0624         if (!amdgpu_sriov_vf(adev))
0625             WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
0626 
0627         /* Set ring buffer size in dwords */
0628         rb_bufsz = order_base_2(ring->ring_size / 4);
0629         rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
0630         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
0631 #ifdef __BIG_ENDIAN
0632         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
0633         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
0634                     RPTR_WRITEBACK_SWAP_ENABLE, 1);
0635 #endif
0636         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
0637 
0638         /* Initialize the ring buffer's read and write pointers */
0639         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
0640         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
0641         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
0642         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
0643 
0644         /* setup the wptr shadow polling */
0645         wptr_gpu_addr = ring->wptr_gpu_addr;
0646         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
0647                lower_32_bits(wptr_gpu_addr));
0648         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
0649                upper_32_bits(wptr_gpu_addr));
0650         wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
0651                              mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
0652         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
0653                            SDMA0_GFX_RB_WPTR_POLL_CNTL,
0654                            F32_POLL_ENABLE, 1);
0655         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
0656                wptr_poll_cntl);
0657 
0658         /* set the wb address whether it's enabled or not */
0659         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
0660                upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
0661         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
0662                lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
0663 
0664         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
0665 
0666         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
0667         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
0668 
0669         ring->wptr = 0;
0670 
0671         /* before programing wptr to a less value, need set minor_ptr_update first */
0672         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
0673 
0674         if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
0675             WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
0676             WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
0677         }
0678 
0679         doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
0680         doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
0681 
0682         if (ring->use_doorbell) {
0683             doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
0684             doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
0685                     OFFSET, ring->doorbell_index);
0686         } else {
0687             doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
0688         }
0689         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
0690         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
0691 
0692         adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
0693                               ring->doorbell_index,
0694                               adev->doorbell_index.sdma_doorbell_range);
0695 
0696         if (amdgpu_sriov_vf(adev))
0697             sdma_v5_2_ring_set_wptr(ring);
0698 
0699         /* set minor_ptr_update to 0 after wptr programed */
0700 
0701         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
0702 
0703         /* SRIOV VF has no control of any of registers below */
0704         if (!amdgpu_sriov_vf(adev)) {
0705             /* set utc l1 enable flag always to 1 */
0706             temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
0707             temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
0708 
0709             /* enable MCBP */
0710             temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
0711             WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
0712 
0713             /* Set up RESP_MODE to non-copy addresses */
0714             temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
0715             temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
0716             temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
0717             WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
0718 
0719             /* program default cache read and write policy */
0720             temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
0721             /* clean read policy and write policy bits */
0722             temp &= 0xFF0FFF;
0723             temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
0724                  (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
0725                  SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
0726             WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
0727 
0728             /* unhalt engine */
0729             temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
0730             temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
0731             WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
0732         }
0733 
0734         /* enable DMA RB */
0735         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
0736         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
0737 
0738         ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
0739         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
0740 #ifdef __BIG_ENDIAN
0741         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
0742 #endif
0743         /* enable DMA IBs */
0744         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
0745 
0746         ring->sched.ready = true;
0747 
0748         if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
0749             sdma_v5_2_ctx_switch_enable(adev, true);
0750             sdma_v5_2_enable(adev, true);
0751         }
0752 
0753         r = amdgpu_ring_test_ring(ring);
0754         if (r) {
0755             ring->sched.ready = false;
0756             return r;
0757         }
0758 
0759         if (adev->mman.buffer_funcs_ring == ring)
0760             amdgpu_ttm_set_buffer_funcs_status(adev, true);
0761     }
0762 
0763     return 0;
0764 }
0765 
0766 /**
0767  * sdma_v5_2_rlc_resume - setup and start the async dma engines
0768  *
0769  * @adev: amdgpu_device pointer
0770  *
0771  * Set up the compute DMA queues and enable them.
0772  * Returns 0 for success, error for failure.
0773  */
0774 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
0775 {
0776     return 0;
0777 }
0778 
0779 /**
0780  * sdma_v5_2_load_microcode - load the sDMA ME ucode
0781  *
0782  * @adev: amdgpu_device pointer
0783  *
0784  * Loads the sDMA0/1/2/3 ucode.
0785  * Returns 0 for success, -EINVAL if the ucode is not available.
0786  */
0787 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
0788 {
0789     const struct sdma_firmware_header_v1_0 *hdr;
0790     const __le32 *fw_data;
0791     u32 fw_size;
0792     int i, j;
0793 
0794     /* halt the MEs */
0795     sdma_v5_2_enable(adev, false);
0796 
0797     for (i = 0; i < adev->sdma.num_instances; i++) {
0798         if (!adev->sdma.instance[i].fw)
0799             return -EINVAL;
0800 
0801         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
0802         amdgpu_ucode_print_sdma_hdr(&hdr->header);
0803         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
0804 
0805         fw_data = (const __le32 *)
0806             (adev->sdma.instance[i].fw->data +
0807                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
0808 
0809         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
0810 
0811         for (j = 0; j < fw_size; j++) {
0812             if (amdgpu_emu_mode == 1 && j % 500 == 0)
0813                 msleep(1);
0814             WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
0815         }
0816 
0817         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
0818     }
0819 
0820     return 0;
0821 }
0822 
0823 static int sdma_v5_2_soft_reset(void *handle)
0824 {
0825     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0826     u32 grbm_soft_reset;
0827     u32 tmp;
0828     int i;
0829 
0830     for (i = 0; i < adev->sdma.num_instances; i++) {
0831         grbm_soft_reset = REG_SET_FIELD(0,
0832                         GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
0833                         1);
0834         grbm_soft_reset <<= i;
0835 
0836         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
0837         tmp |= grbm_soft_reset;
0838         DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
0839         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
0840         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
0841 
0842         udelay(50);
0843 
0844         tmp &= ~grbm_soft_reset;
0845         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
0846         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
0847 
0848         udelay(50);
0849     }
0850 
0851     return 0;
0852 }
0853 
0854 /**
0855  * sdma_v5_2_start - setup and start the async dma engines
0856  *
0857  * @adev: amdgpu_device pointer
0858  *
0859  * Set up the DMA engines and enable them.
0860  * Returns 0 for success, error for failure.
0861  */
0862 static int sdma_v5_2_start(struct amdgpu_device *adev)
0863 {
0864     int r = 0;
0865 
0866     if (amdgpu_sriov_vf(adev)) {
0867         sdma_v5_2_ctx_switch_enable(adev, false);
0868         sdma_v5_2_enable(adev, false);
0869 
0870         /* set RB registers */
0871         r = sdma_v5_2_gfx_resume(adev);
0872         return r;
0873     }
0874 
0875     if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
0876         r = sdma_v5_2_load_microcode(adev);
0877         if (r)
0878             return r;
0879 
0880         /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
0881         if (amdgpu_emu_mode == 1)
0882             msleep(1000);
0883     }
0884 
0885     /* TODO: check whether can submit a doorbell request to raise
0886      * a doorbell fence to exit gfxoff.
0887      */
0888     if (adev->in_s0ix)
0889         amdgpu_gfx_off_ctrl(adev, false);
0890 
0891     sdma_v5_2_soft_reset(adev);
0892     /* unhalt the MEs */
0893     sdma_v5_2_enable(adev, true);
0894     /* enable sdma ring preemption */
0895     sdma_v5_2_ctx_switch_enable(adev, true);
0896 
0897     /* start the gfx rings and rlc compute queues */
0898     r = sdma_v5_2_gfx_resume(adev);
0899     if (adev->in_s0ix)
0900         amdgpu_gfx_off_ctrl(adev, true);
0901     if (r)
0902         return r;
0903     r = sdma_v5_2_rlc_resume(adev);
0904 
0905     return r;
0906 }
0907 
0908 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
0909                   struct amdgpu_mqd_prop *prop)
0910 {
0911     struct v10_sdma_mqd *m = mqd;
0912     uint64_t wb_gpu_addr;
0913 
0914     m->sdmax_rlcx_rb_cntl =
0915         order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
0916         1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
0917         6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
0918         1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
0919 
0920     m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
0921     m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
0922 
0923     m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
0924                           mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
0925 
0926     wb_gpu_addr = prop->wptr_gpu_addr;
0927     m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
0928     m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
0929 
0930     wb_gpu_addr = prop->rptr_gpu_addr;
0931     m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
0932     m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
0933 
0934     m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
0935                             mmSDMA0_GFX_IB_CNTL));
0936 
0937     m->sdmax_rlcx_doorbell_offset =
0938         prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
0939 
0940     m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
0941 
0942     return 0;
0943 }
0944 
0945 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
0946 {
0947     adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
0948     adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
0949 }
0950 
0951 /**
0952  * sdma_v5_2_ring_test_ring - simple async dma engine test
0953  *
0954  * @ring: amdgpu_ring structure holding ring information
0955  *
0956  * Test the DMA engine by writing using it to write an
0957  * value to memory.
0958  * Returns 0 for success, error for failure.
0959  */
0960 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
0961 {
0962     struct amdgpu_device *adev = ring->adev;
0963     unsigned i;
0964     unsigned index;
0965     int r;
0966     u32 tmp;
0967     u64 gpu_addr;
0968     volatile uint32_t *cpu_ptr = NULL;
0969 
0970     tmp = 0xCAFEDEAD;
0971 
0972     if (ring->is_mes_queue) {
0973         uint32_t offset = 0;
0974         offset = amdgpu_mes_ctx_get_offs(ring,
0975                      AMDGPU_MES_CTX_PADDING_OFFS);
0976         gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
0977         cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
0978         *cpu_ptr = tmp;
0979     } else {
0980         r = amdgpu_device_wb_get(adev, &index);
0981         if (r) {
0982             dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
0983             return r;
0984         }
0985 
0986         gpu_addr = adev->wb.gpu_addr + (index * 4);
0987         adev->wb.wb[index] = cpu_to_le32(tmp);
0988     }
0989 
0990     r = amdgpu_ring_alloc(ring, 20);
0991     if (r) {
0992         DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
0993         amdgpu_device_wb_free(adev, index);
0994         return r;
0995     }
0996 
0997     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
0998               SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
0999     amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1000     amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1001     amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1002     amdgpu_ring_write(ring, 0xDEADBEEF);
1003     amdgpu_ring_commit(ring);
1004 
1005     for (i = 0; i < adev->usec_timeout; i++) {
1006         if (ring->is_mes_queue)
1007             tmp = le32_to_cpu(*cpu_ptr);
1008         else
1009             tmp = le32_to_cpu(adev->wb.wb[index]);
1010         if (tmp == 0xDEADBEEF)
1011             break;
1012         if (amdgpu_emu_mode == 1)
1013             msleep(1);
1014         else
1015             udelay(1);
1016     }
1017 
1018     if (i >= adev->usec_timeout)
1019         r = -ETIMEDOUT;
1020 
1021     if (!ring->is_mes_queue)
1022         amdgpu_device_wb_free(adev, index);
1023 
1024     return r;
1025 }
1026 
1027 /**
1028  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
1029  *
1030  * @ring: amdgpu_ring structure holding ring information
1031  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1032  *
1033  * Test a simple IB in the DMA ring.
1034  * Returns 0 on success, error on failure.
1035  */
1036 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1037 {
1038     struct amdgpu_device *adev = ring->adev;
1039     struct amdgpu_ib ib;
1040     struct dma_fence *f = NULL;
1041     unsigned index;
1042     long r;
1043     u32 tmp = 0;
1044     u64 gpu_addr;
1045     volatile uint32_t *cpu_ptr = NULL;
1046 
1047     tmp = 0xCAFEDEAD;
1048     memset(&ib, 0, sizeof(ib));
1049 
1050     if (ring->is_mes_queue) {
1051         uint32_t offset = 0;
1052         offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1053         ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1054         ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1055 
1056         offset = amdgpu_mes_ctx_get_offs(ring,
1057                      AMDGPU_MES_CTX_PADDING_OFFS);
1058         gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1059         cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1060         *cpu_ptr = tmp;
1061     } else {
1062         r = amdgpu_device_wb_get(adev, &index);
1063         if (r) {
1064             dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1065             return r;
1066         }
1067 
1068         gpu_addr = adev->wb.gpu_addr + (index * 4);
1069         adev->wb.wb[index] = cpu_to_le32(tmp);
1070 
1071         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1072         if (r) {
1073             DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1074             goto err0;
1075         }
1076     }
1077 
1078     ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1079         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1080     ib.ptr[1] = lower_32_bits(gpu_addr);
1081     ib.ptr[2] = upper_32_bits(gpu_addr);
1082     ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1083     ib.ptr[4] = 0xDEADBEEF;
1084     ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1085     ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1086     ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1087     ib.length_dw = 8;
1088 
1089     r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1090     if (r)
1091         goto err1;
1092 
1093     r = dma_fence_wait_timeout(f, false, timeout);
1094     if (r == 0) {
1095         DRM_ERROR("amdgpu: IB test timed out\n");
1096         r = -ETIMEDOUT;
1097         goto err1;
1098     } else if (r < 0) {
1099         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1100         goto err1;
1101     }
1102 
1103     if (ring->is_mes_queue)
1104         tmp = le32_to_cpu(*cpu_ptr);
1105     else
1106         tmp = le32_to_cpu(adev->wb.wb[index]);
1107 
1108     if (tmp == 0xDEADBEEF)
1109         r = 0;
1110     else
1111         r = -EINVAL;
1112 
1113 err1:
1114     amdgpu_ib_free(adev, &ib, NULL);
1115     dma_fence_put(f);
1116 err0:
1117     if (!ring->is_mes_queue)
1118         amdgpu_device_wb_free(adev, index);
1119     return r;
1120 }
1121 
1122 
1123 /**
1124  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1125  *
1126  * @ib: indirect buffer to fill with commands
1127  * @pe: addr of the page entry
1128  * @src: src addr to copy from
1129  * @count: number of page entries to update
1130  *
1131  * Update PTEs by copying them from the GART using sDMA.
1132  */
1133 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1134                   uint64_t pe, uint64_t src,
1135                   unsigned count)
1136 {
1137     unsigned bytes = count * 8;
1138 
1139     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1140         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1141     ib->ptr[ib->length_dw++] = bytes - 1;
1142     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1143     ib->ptr[ib->length_dw++] = lower_32_bits(src);
1144     ib->ptr[ib->length_dw++] = upper_32_bits(src);
1145     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1146     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1147 
1148 }
1149 
1150 /**
1151  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1152  *
1153  * @ib: indirect buffer to fill with commands
1154  * @pe: addr of the page entry
1155  * @value: dst addr to write into pe
1156  * @count: number of page entries to update
1157  * @incr: increase next addr by incr bytes
1158  *
1159  * Update PTEs by writing them manually using sDMA.
1160  */
1161 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1162                    uint64_t value, unsigned count,
1163                    uint32_t incr)
1164 {
1165     unsigned ndw = count * 2;
1166 
1167     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1168         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1169     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1170     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1171     ib->ptr[ib->length_dw++] = ndw - 1;
1172     for (; ndw > 0; ndw -= 2) {
1173         ib->ptr[ib->length_dw++] = lower_32_bits(value);
1174         ib->ptr[ib->length_dw++] = upper_32_bits(value);
1175         value += incr;
1176     }
1177 }
1178 
1179 /**
1180  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1181  *
1182  * @ib: indirect buffer to fill with commands
1183  * @pe: addr of the page entry
1184  * @addr: dst addr to write into pe
1185  * @count: number of page entries to update
1186  * @incr: increase next addr by incr bytes
1187  * @flags: access flags
1188  *
1189  * Update the page tables using sDMA.
1190  */
1191 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1192                      uint64_t pe,
1193                      uint64_t addr, unsigned count,
1194                      uint32_t incr, uint64_t flags)
1195 {
1196     /* for physically contiguous pages (vram) */
1197     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1198     ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1199     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1200     ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1201     ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1202     ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1203     ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1204     ib->ptr[ib->length_dw++] = incr; /* increment size */
1205     ib->ptr[ib->length_dw++] = 0;
1206     ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1207 }
1208 
1209 /**
1210  * sdma_v5_2_ring_pad_ib - pad the IB
1211  *
1212  * @ib: indirect buffer to fill with padding
1213  * @ring: amdgpu_ring structure holding ring information
1214  *
1215  * Pad the IB with NOPs to a boundary multiple of 8.
1216  */
1217 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1218 {
1219     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1220     u32 pad_count;
1221     int i;
1222 
1223     pad_count = (-ib->length_dw) & 0x7;
1224     for (i = 0; i < pad_count; i++)
1225         if (sdma && sdma->burst_nop && (i == 0))
1226             ib->ptr[ib->length_dw++] =
1227                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1228                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1229         else
1230             ib->ptr[ib->length_dw++] =
1231                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1232 }
1233 
1234 
1235 /**
1236  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1237  *
1238  * @ring: amdgpu_ring pointer
1239  *
1240  * Make sure all previous operations are completed (CIK).
1241  */
1242 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1243 {
1244     uint32_t seq = ring->fence_drv.sync_seq;
1245     uint64_t addr = ring->fence_drv.gpu_addr;
1246 
1247     /* wait for idle */
1248     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1249               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1250               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1251               SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1252     amdgpu_ring_write(ring, addr & 0xfffffffc);
1253     amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1254     amdgpu_ring_write(ring, seq); /* reference */
1255     amdgpu_ring_write(ring, 0xffffffff); /* mask */
1256     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1257               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1258 }
1259 
1260 
1261 /**
1262  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1263  *
1264  * @ring: amdgpu_ring pointer
1265  * @vmid: vmid number to use
1266  * @pd_addr: address
1267  *
1268  * Update the page table base and flush the VM TLB
1269  * using sDMA.
1270  */
1271 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1272                      unsigned vmid, uint64_t pd_addr)
1273 {
1274     amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1275 }
1276 
1277 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1278                      uint32_t reg, uint32_t val)
1279 {
1280     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1281               SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1282     amdgpu_ring_write(ring, reg);
1283     amdgpu_ring_write(ring, val);
1284 }
1285 
1286 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1287                      uint32_t val, uint32_t mask)
1288 {
1289     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1290               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1291               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1292     amdgpu_ring_write(ring, reg << 2);
1293     amdgpu_ring_write(ring, 0);
1294     amdgpu_ring_write(ring, val); /* reference */
1295     amdgpu_ring_write(ring, mask); /* mask */
1296     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1297               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1298 }
1299 
1300 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1301                            uint32_t reg0, uint32_t reg1,
1302                            uint32_t ref, uint32_t mask)
1303 {
1304     amdgpu_ring_emit_wreg(ring, reg0, ref);
1305     /* wait for a cycle to reset vm_inv_eng*_ack */
1306     amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1307     amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1308 }
1309 
1310 static int sdma_v5_2_early_init(void *handle)
1311 {
1312     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313 
1314     sdma_v5_2_set_ring_funcs(adev);
1315     sdma_v5_2_set_buffer_funcs(adev);
1316     sdma_v5_2_set_vm_pte_funcs(adev);
1317     sdma_v5_2_set_irq_funcs(adev);
1318     sdma_v5_2_set_mqd_funcs(adev);
1319 
1320     return 0;
1321 }
1322 
1323 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1324 {
1325     switch (seq_num) {
1326     case 0:
1327         return SOC15_IH_CLIENTID_SDMA0;
1328     case 1:
1329         return SOC15_IH_CLIENTID_SDMA1;
1330     case 2:
1331         return SOC15_IH_CLIENTID_SDMA2;
1332     case 3:
1333         return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1334     default:
1335         break;
1336     }
1337     return -EINVAL;
1338 }
1339 
1340 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1341 {
1342     switch (seq_num) {
1343     case 0:
1344         return SDMA0_5_0__SRCID__SDMA_TRAP;
1345     case 1:
1346         return SDMA1_5_0__SRCID__SDMA_TRAP;
1347     case 2:
1348         return SDMA2_5_0__SRCID__SDMA_TRAP;
1349     case 3:
1350         return SDMA3_5_0__SRCID__SDMA_TRAP;
1351     default:
1352         break;
1353     }
1354     return -EINVAL;
1355 }
1356 
1357 static int sdma_v5_2_sw_init(void *handle)
1358 {
1359     struct amdgpu_ring *ring;
1360     int r, i;
1361     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362 
1363     /* SDMA trap event */
1364     for (i = 0; i < adev->sdma.num_instances; i++) {
1365         r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1366                       sdma_v5_2_seq_to_trap_id(i),
1367                       &adev->sdma.trap_irq);
1368         if (r)
1369             return r;
1370     }
1371 
1372     r = sdma_v5_2_init_microcode(adev);
1373     if (r) {
1374         DRM_ERROR("Failed to load sdma firmware!\n");
1375         return r;
1376     }
1377 
1378     for (i = 0; i < adev->sdma.num_instances; i++) {
1379         ring = &adev->sdma.instance[i].ring;
1380         ring->ring_obj = NULL;
1381         ring->use_doorbell = true;
1382         ring->me = i;
1383 
1384         DRM_INFO("use_doorbell being set to: [%s]\n",
1385                 ring->use_doorbell?"true":"false");
1386 
1387         ring->doorbell_index =
1388             (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1389 
1390         sprintf(ring->name, "sdma%d", i);
1391         r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1392                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1393                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1394         if (r)
1395             return r;
1396     }
1397 
1398     return r;
1399 }
1400 
1401 static int sdma_v5_2_sw_fini(void *handle)
1402 {
1403     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1404     int i;
1405 
1406     for (i = 0; i < adev->sdma.num_instances; i++)
1407         amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1408 
1409     sdma_v5_2_destroy_inst_ctx(adev);
1410 
1411     return 0;
1412 }
1413 
1414 static int sdma_v5_2_hw_init(void *handle)
1415 {
1416     int r;
1417     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1418 
1419     r = sdma_v5_2_start(adev);
1420 
1421     return r;
1422 }
1423 
1424 static int sdma_v5_2_hw_fini(void *handle)
1425 {
1426     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1427 
1428     if (amdgpu_sriov_vf(adev))
1429         return 0;
1430 
1431     sdma_v5_2_ctx_switch_enable(adev, false);
1432     sdma_v5_2_enable(adev, false);
1433 
1434     return 0;
1435 }
1436 
1437 static int sdma_v5_2_suspend(void *handle)
1438 {
1439     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1440 
1441     return sdma_v5_2_hw_fini(adev);
1442 }
1443 
1444 static int sdma_v5_2_resume(void *handle)
1445 {
1446     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1447 
1448     return sdma_v5_2_hw_init(adev);
1449 }
1450 
1451 static bool sdma_v5_2_is_idle(void *handle)
1452 {
1453     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1454     u32 i;
1455 
1456     for (i = 0; i < adev->sdma.num_instances; i++) {
1457         u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1458 
1459         if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1460             return false;
1461     }
1462 
1463     return true;
1464 }
1465 
1466 static int sdma_v5_2_wait_for_idle(void *handle)
1467 {
1468     unsigned i;
1469     u32 sdma0, sdma1, sdma2, sdma3;
1470     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1471 
1472     for (i = 0; i < adev->usec_timeout; i++) {
1473         sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1474         sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1475         sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1476         sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1477 
1478         if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1479             return 0;
1480         udelay(1);
1481     }
1482     return -ETIMEDOUT;
1483 }
1484 
1485 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1486 {
1487     int i, r = 0;
1488     struct amdgpu_device *adev = ring->adev;
1489     u32 index = 0;
1490     u64 sdma_gfx_preempt;
1491 
1492     amdgpu_sdma_get_index_from_ring(ring, &index);
1493     sdma_gfx_preempt =
1494         sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1495 
1496     /* assert preemption condition */
1497     amdgpu_ring_set_preempt_cond_exec(ring, false);
1498 
1499     /* emit the trailing fence */
1500     ring->trail_seq += 1;
1501     amdgpu_ring_alloc(ring, 10);
1502     sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1503                   ring->trail_seq, 0);
1504     amdgpu_ring_commit(ring);
1505 
1506     /* assert IB preemption */
1507     WREG32(sdma_gfx_preempt, 1);
1508 
1509     /* poll the trailing fence */
1510     for (i = 0; i < adev->usec_timeout; i++) {
1511         if (ring->trail_seq ==
1512             le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1513             break;
1514         udelay(1);
1515     }
1516 
1517     if (i >= adev->usec_timeout) {
1518         r = -EINVAL;
1519         DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1520     }
1521 
1522     /* deassert IB preemption */
1523     WREG32(sdma_gfx_preempt, 0);
1524 
1525     /* deassert the preemption condition */
1526     amdgpu_ring_set_preempt_cond_exec(ring, true);
1527     return r;
1528 }
1529 
1530 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1531                     struct amdgpu_irq_src *source,
1532                     unsigned type,
1533                     enum amdgpu_interrupt_state state)
1534 {
1535     u32 sdma_cntl;
1536     u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1537 
1538     if (!amdgpu_sriov_vf(adev)) {
1539         sdma_cntl = RREG32(reg_offset);
1540         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1541                    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1542         WREG32(reg_offset, sdma_cntl);
1543     }
1544 
1545     return 0;
1546 }
1547 
1548 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1549                       struct amdgpu_irq_src *source,
1550                       struct amdgpu_iv_entry *entry)
1551 {
1552     uint32_t mes_queue_id = entry->src_data[0];
1553 
1554     DRM_DEBUG("IH: SDMA trap\n");
1555 
1556     if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1557         struct amdgpu_mes_queue *queue;
1558 
1559         mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1560 
1561         spin_lock(&adev->mes.queue_id_lock);
1562         queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1563         if (queue) {
1564             DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1565             amdgpu_fence_process(queue->ring);
1566         }
1567         spin_unlock(&adev->mes.queue_id_lock);
1568         return 0;
1569     }
1570 
1571     switch (entry->client_id) {
1572     case SOC15_IH_CLIENTID_SDMA0:
1573         switch (entry->ring_id) {
1574         case 0:
1575             amdgpu_fence_process(&adev->sdma.instance[0].ring);
1576             break;
1577         case 1:
1578             /* XXX compute */
1579             break;
1580         case 2:
1581             /* XXX compute */
1582             break;
1583         case 3:
1584             /* XXX page queue*/
1585             break;
1586         }
1587         break;
1588     case SOC15_IH_CLIENTID_SDMA1:
1589         switch (entry->ring_id) {
1590         case 0:
1591             amdgpu_fence_process(&adev->sdma.instance[1].ring);
1592             break;
1593         case 1:
1594             /* XXX compute */
1595             break;
1596         case 2:
1597             /* XXX compute */
1598             break;
1599         case 3:
1600             /* XXX page queue*/
1601             break;
1602         }
1603         break;
1604     case SOC15_IH_CLIENTID_SDMA2:
1605         switch (entry->ring_id) {
1606         case 0:
1607             amdgpu_fence_process(&adev->sdma.instance[2].ring);
1608             break;
1609         case 1:
1610             /* XXX compute */
1611             break;
1612         case 2:
1613             /* XXX compute */
1614             break;
1615         case 3:
1616             /* XXX page queue*/
1617             break;
1618         }
1619         break;
1620     case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1621         switch (entry->ring_id) {
1622         case 0:
1623             amdgpu_fence_process(&adev->sdma.instance[3].ring);
1624             break;
1625         case 1:
1626             /* XXX compute */
1627             break;
1628         case 2:
1629             /* XXX compute */
1630             break;
1631         case 3:
1632             /* XXX page queue*/
1633             break;
1634         }
1635         break;
1636     }
1637     return 0;
1638 }
1639 
1640 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1641                           struct amdgpu_irq_src *source,
1642                           struct amdgpu_iv_entry *entry)
1643 {
1644     return 0;
1645 }
1646 
1647 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1648                                bool enable)
1649 {
1650     uint32_t data, def;
1651     int i;
1652 
1653     for (i = 0; i < adev->sdma.num_instances; i++) {
1654 
1655         if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1656             adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1657 
1658         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1659             /* Enable sdma clock gating */
1660             def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1661             data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1662                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1663                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1664                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1665                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1666                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1667             if (def != data)
1668                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1669         } else {
1670             /* Disable sdma clock gating */
1671             def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1672             data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1673                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1674                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1675                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1676                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1677                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1678             if (def != data)
1679                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1680         }
1681     }
1682 }
1683 
1684 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1685                               bool enable)
1686 {
1687     uint32_t data, def;
1688     int i;
1689 
1690     for (i = 0; i < adev->sdma.num_instances; i++) {
1691 
1692         if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1693             adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1694 
1695         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1696             /* Enable sdma mem light sleep */
1697             def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1698             data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1699             if (def != data)
1700                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1701 
1702         } else {
1703             /* Disable sdma mem light sleep */
1704             def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1705             data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1706             if (def != data)
1707                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1708 
1709         }
1710     }
1711 }
1712 
1713 static int sdma_v5_2_set_clockgating_state(void *handle,
1714                        enum amd_clockgating_state state)
1715 {
1716     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1717 
1718     if (amdgpu_sriov_vf(adev))
1719         return 0;
1720 
1721     switch (adev->ip_versions[SDMA0_HWIP][0]) {
1722     case IP_VERSION(5, 2, 0):
1723     case IP_VERSION(5, 2, 2):
1724     case IP_VERSION(5, 2, 1):
1725     case IP_VERSION(5, 2, 4):
1726     case IP_VERSION(5, 2, 5):
1727     case IP_VERSION(5, 2, 6):
1728     case IP_VERSION(5, 2, 3):
1729         sdma_v5_2_update_medium_grain_clock_gating(adev,
1730                 state == AMD_CG_STATE_GATE);
1731         sdma_v5_2_update_medium_grain_light_sleep(adev,
1732                 state == AMD_CG_STATE_GATE);
1733         break;
1734     default:
1735         break;
1736     }
1737 
1738     return 0;
1739 }
1740 
1741 static int sdma_v5_2_set_powergating_state(void *handle,
1742                       enum amd_powergating_state state)
1743 {
1744     return 0;
1745 }
1746 
1747 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
1748 {
1749     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1750     int data;
1751 
1752     if (amdgpu_sriov_vf(adev))
1753         *flags = 0;
1754 
1755     /* AMD_CG_SUPPORT_SDMA_MGCG */
1756     data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1757     if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1758         *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1759 
1760     /* AMD_CG_SUPPORT_SDMA_LS */
1761     data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1762     if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1763         *flags |= AMD_CG_SUPPORT_SDMA_LS;
1764 }
1765 
1766 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1767     .name = "sdma_v5_2",
1768     .early_init = sdma_v5_2_early_init,
1769     .late_init = NULL,
1770     .sw_init = sdma_v5_2_sw_init,
1771     .sw_fini = sdma_v5_2_sw_fini,
1772     .hw_init = sdma_v5_2_hw_init,
1773     .hw_fini = sdma_v5_2_hw_fini,
1774     .suspend = sdma_v5_2_suspend,
1775     .resume = sdma_v5_2_resume,
1776     .is_idle = sdma_v5_2_is_idle,
1777     .wait_for_idle = sdma_v5_2_wait_for_idle,
1778     .soft_reset = sdma_v5_2_soft_reset,
1779     .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1780     .set_powergating_state = sdma_v5_2_set_powergating_state,
1781     .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1782 };
1783 
1784 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1785     .type = AMDGPU_RING_TYPE_SDMA,
1786     .align_mask = 0xf,
1787     .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1788     .support_64bit_ptrs = true,
1789     .secure_submission_supported = true,
1790     .vmhub = AMDGPU_GFXHUB_0,
1791     .get_rptr = sdma_v5_2_ring_get_rptr,
1792     .get_wptr = sdma_v5_2_ring_get_wptr,
1793     .set_wptr = sdma_v5_2_ring_set_wptr,
1794     .emit_frame_size =
1795         5 + /* sdma_v5_2_ring_init_cond_exec */
1796         6 + /* sdma_v5_2_ring_emit_hdp_flush */
1797         3 + /* hdp_invalidate */
1798         6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1799         /* sdma_v5_2_ring_emit_vm_flush */
1800         SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1801         SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1802         10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1803     .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1804     .emit_ib = sdma_v5_2_ring_emit_ib,
1805     .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1806     .emit_fence = sdma_v5_2_ring_emit_fence,
1807     .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1808     .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1809     .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1810     .test_ring = sdma_v5_2_ring_test_ring,
1811     .test_ib = sdma_v5_2_ring_test_ib,
1812     .insert_nop = sdma_v5_2_ring_insert_nop,
1813     .pad_ib = sdma_v5_2_ring_pad_ib,
1814     .emit_wreg = sdma_v5_2_ring_emit_wreg,
1815     .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1816     .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1817     .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1818     .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1819     .preempt_ib = sdma_v5_2_ring_preempt_ib,
1820 };
1821 
1822 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1823 {
1824     int i;
1825 
1826     for (i = 0; i < adev->sdma.num_instances; i++) {
1827         adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1828         adev->sdma.instance[i].ring.me = i;
1829     }
1830 }
1831 
1832 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1833     .set = sdma_v5_2_set_trap_irq_state,
1834     .process = sdma_v5_2_process_trap_irq,
1835 };
1836 
1837 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1838     .process = sdma_v5_2_process_illegal_inst_irq,
1839 };
1840 
1841 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1842 {
1843     adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1844                     adev->sdma.num_instances;
1845     adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1846     adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1847 }
1848 
1849 /**
1850  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1851  *
1852  * @ib: indirect buffer to copy to
1853  * @src_offset: src GPU address
1854  * @dst_offset: dst GPU address
1855  * @byte_count: number of bytes to xfer
1856  * @tmz: if a secure copy should be used
1857  *
1858  * Copy GPU buffers using the DMA engine.
1859  * Used by the amdgpu ttm implementation to move pages if
1860  * registered as the asic copy callback.
1861  */
1862 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1863                        uint64_t src_offset,
1864                        uint64_t dst_offset,
1865                        uint32_t byte_count,
1866                        bool tmz)
1867 {
1868     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1869         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1870         SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1871     ib->ptr[ib->length_dw++] = byte_count - 1;
1872     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1873     ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1874     ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1875     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1876     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1877 }
1878 
1879 /**
1880  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1881  *
1882  * @ib: indirect buffer to fill
1883  * @src_data: value to write to buffer
1884  * @dst_offset: dst GPU address
1885  * @byte_count: number of bytes to xfer
1886  *
1887  * Fill GPU buffers using the DMA engine.
1888  */
1889 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1890                        uint32_t src_data,
1891                        uint64_t dst_offset,
1892                        uint32_t byte_count)
1893 {
1894     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1895     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1896     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1897     ib->ptr[ib->length_dw++] = src_data;
1898     ib->ptr[ib->length_dw++] = byte_count - 1;
1899 }
1900 
1901 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1902     .copy_max_bytes = 0x400000,
1903     .copy_num_dw = 7,
1904     .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1905 
1906     .fill_max_bytes = 0x400000,
1907     .fill_num_dw = 5,
1908     .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1909 };
1910 
1911 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1912 {
1913     if (adev->mman.buffer_funcs == NULL) {
1914         adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1915         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1916     }
1917 }
1918 
1919 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1920     .copy_pte_num_dw = 7,
1921     .copy_pte = sdma_v5_2_vm_copy_pte,
1922     .write_pte = sdma_v5_2_vm_write_pte,
1923     .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1924 };
1925 
1926 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1927 {
1928     unsigned i;
1929 
1930     if (adev->vm_manager.vm_pte_funcs == NULL) {
1931         adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1932         for (i = 0; i < adev->sdma.num_instances; i++) {
1933             adev->vm_manager.vm_pte_scheds[i] =
1934                 &adev->sdma.instance[i].ring.sched;
1935         }
1936         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1937     }
1938 }
1939 
1940 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1941     .type = AMD_IP_BLOCK_TYPE_SDMA,
1942     .major = 5,
1943     .minor = 2,
1944     .rev = 0,
1945     .funcs = &sdma_v5_2_ip_funcs,
1946 };
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