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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <linux/delay.h>
0025 #include <linux/firmware.h>
0026 #include <linux/module.h>
0027 #include <linux/pci.h>
0028 
0029 #include "amdgpu.h"
0030 #include "amdgpu_ucode.h"
0031 #include "amdgpu_trace.h"
0032 
0033 #include "gc/gc_10_1_0_offset.h"
0034 #include "gc/gc_10_1_0_sh_mask.h"
0035 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
0036 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
0037 
0038 #include "soc15_common.h"
0039 #include "soc15.h"
0040 #include "navi10_sdma_pkt_open.h"
0041 #include "nbio_v2_3.h"
0042 #include "sdma_common.h"
0043 #include "sdma_v5_0.h"
0044 
0045 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
0046 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
0047 
0048 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
0049 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
0050 
0051 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
0052 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
0053 
0054 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
0055 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
0056 
0057 #define SDMA1_REG_OFFSET 0x600
0058 #define SDMA0_HYP_DEC_REG_START 0x5880
0059 #define SDMA0_HYP_DEC_REG_END 0x5893
0060 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
0061 
0062 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
0063 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
0064 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
0065 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
0066 
0067 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
0068     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
0069     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0070     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0071     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0072     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0073     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0074     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0075     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0076     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0077     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0078     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0079     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
0080     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
0081     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0082     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0083     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0084     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0085     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0086     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0087     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0088     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0089     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0090     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0091     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
0092 };
0093 
0094 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
0095     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0096     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0097     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0098     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0099     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0100     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0101     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0102     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0103     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0104     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0105     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0106     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0107     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0108     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0109     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0110     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0111     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0112     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0113     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0114     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0115 };
0116 
0117 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
0118     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
0119     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
0120 };
0121 
0122 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
0123     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0124     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0125 };
0126 
0127 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
0128     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0129     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
0130     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
0131     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
0132     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
0133     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0134 };
0135 
0136 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
0137     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
0138     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
0139     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
0140     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0141     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0142     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0143     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0144     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0145     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0146     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0147     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0148     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0149     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0150     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
0151     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
0152     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
0153     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
0154     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0155     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0156     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0157     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0158     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0159     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0160     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0161     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0162     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0163     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
0164     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
0165 };
0166 
0167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
0168 {
0169     u32 base;
0170 
0171     if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
0172         internal_offset <= SDMA0_HYP_DEC_REG_END) {
0173         base = adev->reg_offset[GC_HWIP][0][1];
0174         if (instance == 1)
0175             internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
0176     } else {
0177         base = adev->reg_offset[GC_HWIP][0][0];
0178         if (instance == 1)
0179             internal_offset += SDMA1_REG_OFFSET;
0180     }
0181 
0182     return base + internal_offset;
0183 }
0184 
0185 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
0186 {
0187     switch (adev->ip_versions[SDMA0_HWIP][0]) {
0188     case IP_VERSION(5, 0, 0):
0189         soc15_program_register_sequence(adev,
0190                         golden_settings_sdma_5,
0191                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
0192         soc15_program_register_sequence(adev,
0193                         golden_settings_sdma_nv10,
0194                         (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
0195         break;
0196     case IP_VERSION(5, 0, 2):
0197         soc15_program_register_sequence(adev,
0198                         golden_settings_sdma_5,
0199                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
0200         soc15_program_register_sequence(adev,
0201                         golden_settings_sdma_nv14,
0202                         (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
0203         break;
0204     case IP_VERSION(5, 0, 5):
0205         if (amdgpu_sriov_vf(adev))
0206             soc15_program_register_sequence(adev,
0207                             golden_settings_sdma_5_sriov,
0208                             (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
0209         else
0210             soc15_program_register_sequence(adev,
0211                             golden_settings_sdma_5,
0212                             (const u32)ARRAY_SIZE(golden_settings_sdma_5));
0213         soc15_program_register_sequence(adev,
0214                         golden_settings_sdma_nv12,
0215                         (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
0216         break;
0217     case IP_VERSION(5, 0, 1):
0218         soc15_program_register_sequence(adev,
0219                         golden_settings_sdma_cyan_skillfish,
0220                         (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
0221         break;
0222     default:
0223         break;
0224     }
0225 }
0226 
0227 /**
0228  * sdma_v5_0_init_microcode - load ucode images from disk
0229  *
0230  * @adev: amdgpu_device pointer
0231  *
0232  * Use the firmware interface to load the ucode images into
0233  * the driver (not loaded into hw).
0234  * Returns 0 on success, error on failure.
0235  */
0236 
0237 // emulation only, won't work on real chip
0238 // navi10 real chip need to use PSP to load firmware
0239 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
0240 {
0241     const char *chip_name;
0242     char fw_name[40];
0243     int err = 0, i;
0244     struct amdgpu_firmware_info *info = NULL;
0245     const struct common_firmware_header *header = NULL;
0246     const struct sdma_firmware_header_v1_0 *hdr;
0247 
0248     if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
0249         return 0;
0250 
0251     DRM_DEBUG("\n");
0252 
0253     switch (adev->ip_versions[SDMA0_HWIP][0]) {
0254     case IP_VERSION(5, 0, 0):
0255         chip_name = "navi10";
0256         break;
0257     case IP_VERSION(5, 0, 2):
0258         chip_name = "navi14";
0259         break;
0260     case IP_VERSION(5, 0, 5):
0261         chip_name = "navi12";
0262         break;
0263     case IP_VERSION(5, 0, 1):
0264         chip_name = "cyan_skillfish2";
0265         break;
0266     default:
0267         BUG();
0268     }
0269 
0270     for (i = 0; i < adev->sdma.num_instances; i++) {
0271         if (i == 0)
0272             snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
0273         else
0274             snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
0275         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
0276         if (err)
0277             goto out;
0278         err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
0279         if (err)
0280             goto out;
0281         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
0282         adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
0283         adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
0284         if (adev->sdma.instance[i].feature_version >= 20)
0285             adev->sdma.instance[i].burst_nop = true;
0286         DRM_DEBUG("psp_load == '%s'\n",
0287                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
0288 
0289         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
0290             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
0291             info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
0292             info->fw = adev->sdma.instance[i].fw;
0293             header = (const struct common_firmware_header *)info->fw->data;
0294             adev->firmware.fw_size +=
0295                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
0296         }
0297     }
0298 out:
0299     if (err) {
0300         DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
0301         for (i = 0; i < adev->sdma.num_instances; i++) {
0302             release_firmware(adev->sdma.instance[i].fw);
0303             adev->sdma.instance[i].fw = NULL;
0304         }
0305     }
0306     return err;
0307 }
0308 
0309 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
0310 {
0311     unsigned ret;
0312 
0313     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
0314     amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
0315     amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
0316     amdgpu_ring_write(ring, 1);
0317     ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
0318     amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
0319 
0320     return ret;
0321 }
0322 
0323 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
0324                        unsigned offset)
0325 {
0326     unsigned cur;
0327 
0328     BUG_ON(offset > ring->buf_mask);
0329     BUG_ON(ring->ring[offset] != 0x55aa55aa);
0330 
0331     cur = (ring->wptr - 1) & ring->buf_mask;
0332     if (cur > offset)
0333         ring->ring[offset] = cur - offset;
0334     else
0335         ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
0336 }
0337 
0338 /**
0339  * sdma_v5_0_ring_get_rptr - get the current read pointer
0340  *
0341  * @ring: amdgpu ring pointer
0342  *
0343  * Get the current rptr from the hardware (NAVI10+).
0344  */
0345 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
0346 {
0347     u64 *rptr;
0348 
0349     /* XXX check if swapping is necessary on BE */
0350     rptr = (u64 *)ring->rptr_cpu_addr;
0351 
0352     DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
0353     return ((*rptr) >> 2);
0354 }
0355 
0356 /**
0357  * sdma_v5_0_ring_get_wptr - get the current write pointer
0358  *
0359  * @ring: amdgpu ring pointer
0360  *
0361  * Get the current wptr from the hardware (NAVI10+).
0362  */
0363 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
0364 {
0365     struct amdgpu_device *adev = ring->adev;
0366     u64 wptr;
0367 
0368     if (ring->use_doorbell) {
0369         /* XXX check if swapping is necessary on BE */
0370         wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
0371         DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
0372     } else {
0373         wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
0374         wptr = wptr << 32;
0375         wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
0376         DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
0377     }
0378 
0379     return wptr >> 2;
0380 }
0381 
0382 /**
0383  * sdma_v5_0_ring_set_wptr - commit the write pointer
0384  *
0385  * @ring: amdgpu ring pointer
0386  *
0387  * Write the wptr back to the hardware (NAVI10+).
0388  */
0389 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
0390 {
0391     struct amdgpu_device *adev = ring->adev;
0392     uint32_t *wptr_saved;
0393     uint32_t *is_queue_unmap;
0394     uint64_t aggregated_db_index;
0395     uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
0396 
0397     DRM_DEBUG("Setting write pointer\n");
0398     if (ring->is_mes_queue) {
0399         wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
0400         is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
0401                           sizeof(uint32_t));
0402         aggregated_db_index =
0403             amdgpu_mes_get_aggregated_doorbell_index(adev,
0404             AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
0405 
0406         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
0407                  ring->wptr << 2);
0408         *wptr_saved = ring->wptr << 2;
0409         if (*is_queue_unmap) {
0410             WDOORBELL64(aggregated_db_index, ring->wptr << 2);
0411             DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
0412                     ring->doorbell_index, ring->wptr << 2);
0413             WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
0414         } else {
0415             DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
0416                     ring->doorbell_index, ring->wptr << 2);
0417             WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
0418 
0419             if (*is_queue_unmap)
0420                 WDOORBELL64(aggregated_db_index,
0421                         ring->wptr << 2);
0422         }
0423     } else {
0424         if (ring->use_doorbell) {
0425             DRM_DEBUG("Using doorbell -- "
0426                   "wptr_offs == 0x%08x "
0427                   "lower_32_bits(ring->wptr) << 2 == 0x%08x "
0428                   "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
0429                   ring->wptr_offs,
0430                   lower_32_bits(ring->wptr << 2),
0431                   upper_32_bits(ring->wptr << 2));
0432             /* XXX check if swapping is necessary on BE */
0433             atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
0434                      ring->wptr << 2);
0435             DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
0436                   ring->doorbell_index, ring->wptr << 2);
0437             WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
0438         } else {
0439             DRM_DEBUG("Not using doorbell -- "
0440                   "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
0441                   "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
0442                   ring->me,
0443                   lower_32_bits(ring->wptr << 2),
0444                   ring->me,
0445                   upper_32_bits(ring->wptr << 2));
0446             WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
0447                          ring->me, mmSDMA0_GFX_RB_WPTR),
0448                     lower_32_bits(ring->wptr << 2));
0449             WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
0450                          ring->me, mmSDMA0_GFX_RB_WPTR_HI),
0451                     upper_32_bits(ring->wptr << 2));
0452         }
0453     }
0454 }
0455 
0456 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
0457 {
0458     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
0459     int i;
0460 
0461     for (i = 0; i < count; i++)
0462         if (sdma && sdma->burst_nop && (i == 0))
0463             amdgpu_ring_write(ring, ring->funcs->nop |
0464                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
0465         else
0466             amdgpu_ring_write(ring, ring->funcs->nop);
0467 }
0468 
0469 /**
0470  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
0471  *
0472  * @ring: amdgpu ring pointer
0473  * @job: job to retrieve vmid from
0474  * @ib: IB object to schedule
0475  * @flags: unused
0476  *
0477  * Schedule an IB in the DMA ring (NAVI10).
0478  */
0479 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
0480                    struct amdgpu_job *job,
0481                    struct amdgpu_ib *ib,
0482                    uint32_t flags)
0483 {
0484     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
0485     uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
0486 
0487     /* An IB packet must end on a 8 DW boundary--the next dword
0488      * must be on a 8-dword boundary. Our IB packet below is 6
0489      * dwords long, thus add x number of NOPs, such that, in
0490      * modular arithmetic,
0491      * wptr + 6 + x = 8k, k >= 0, which in C is,
0492      * (wptr + 6 + x) % 8 = 0.
0493      * The expression below, is a solution of x.
0494      */
0495     sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
0496 
0497     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
0498               SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
0499     /* base must be 32 byte aligned */
0500     amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
0501     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
0502     amdgpu_ring_write(ring, ib->length_dw);
0503     amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
0504     amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
0505 }
0506 
0507 /**
0508  * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
0509  *
0510  * @ring: amdgpu ring pointer
0511  *
0512  * flush the IB by graphics cache rinse.
0513  */
0514 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
0515 {
0516     uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
0517                 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
0518                 SDMA_GCR_GLI_INV(1);
0519 
0520     /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
0521     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
0522     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
0523     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
0524               SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
0525     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
0526               SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
0527     amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
0528               SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
0529 }
0530 
0531 /**
0532  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
0533  *
0534  * @ring: amdgpu ring pointer
0535  *
0536  * Emit an hdp flush packet on the requested DMA ring.
0537  */
0538 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
0539 {
0540     struct amdgpu_device *adev = ring->adev;
0541     u32 ref_and_mask = 0;
0542     const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
0543 
0544     if (ring->me == 0)
0545         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
0546     else
0547         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
0548 
0549     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
0550               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
0551               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
0552     amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
0553     amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
0554     amdgpu_ring_write(ring, ref_and_mask); /* reference */
0555     amdgpu_ring_write(ring, ref_and_mask); /* mask */
0556     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
0557               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
0558 }
0559 
0560 /**
0561  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
0562  *
0563  * @ring: amdgpu ring pointer
0564  * @addr: address
0565  * @seq: sequence number
0566  * @flags: fence related flags
0567  *
0568  * Add a DMA fence packet to the ring to write
0569  * the fence seq number and DMA trap packet to generate
0570  * an interrupt if needed (NAVI10).
0571  */
0572 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0573                       unsigned flags)
0574 {
0575     bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
0576     /* write the fence */
0577     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
0578               SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
0579     /* zero in first two bits */
0580     BUG_ON(addr & 0x3);
0581     amdgpu_ring_write(ring, lower_32_bits(addr));
0582     amdgpu_ring_write(ring, upper_32_bits(addr));
0583     amdgpu_ring_write(ring, lower_32_bits(seq));
0584 
0585     /* optionally write high bits as well */
0586     if (write64bit) {
0587         addr += 4;
0588         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
0589                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
0590         /* zero in first two bits */
0591         BUG_ON(addr & 0x3);
0592         amdgpu_ring_write(ring, lower_32_bits(addr));
0593         amdgpu_ring_write(ring, upper_32_bits(addr));
0594         amdgpu_ring_write(ring, upper_32_bits(seq));
0595     }
0596 
0597     if (flags & AMDGPU_FENCE_FLAG_INT) {
0598         uint32_t ctx = ring->is_mes_queue ?
0599             (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
0600         /* generate an interrupt */
0601         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
0602         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
0603     }
0604 }
0605 
0606 
0607 /**
0608  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
0609  *
0610  * @adev: amdgpu_device pointer
0611  *
0612  * Stop the gfx async dma ring buffers (NAVI10).
0613  */
0614 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
0615 {
0616     struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
0617     struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
0618     u32 rb_cntl, ib_cntl;
0619     int i;
0620 
0621     if ((adev->mman.buffer_funcs_ring == sdma0) ||
0622         (adev->mman.buffer_funcs_ring == sdma1))
0623         amdgpu_ttm_set_buffer_funcs_status(adev, false);
0624 
0625     for (i = 0; i < adev->sdma.num_instances; i++) {
0626         rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
0627         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
0628         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
0629         ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
0630         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
0631         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
0632     }
0633 }
0634 
0635 /**
0636  * sdma_v5_0_rlc_stop - stop the compute async dma engines
0637  *
0638  * @adev: amdgpu_device pointer
0639  *
0640  * Stop the compute async dma queues (NAVI10).
0641  */
0642 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
0643 {
0644     /* XXX todo */
0645 }
0646 
0647 /**
0648  * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
0649  *
0650  * @adev: amdgpu_device pointer
0651  * @enable: enable/disable the DMA MEs context switch.
0652  *
0653  * Halt or unhalt the async dma engines context switch (NAVI10).
0654  */
0655 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
0656 {
0657     u32 f32_cntl = 0, phase_quantum = 0;
0658     int i;
0659 
0660     if (amdgpu_sdma_phase_quantum) {
0661         unsigned value = amdgpu_sdma_phase_quantum;
0662         unsigned unit = 0;
0663 
0664         while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0665                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
0666             value = (value + 1) >> 1;
0667             unit++;
0668         }
0669         if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0670                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
0671             value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0672                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
0673             unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0674                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
0675             WARN_ONCE(1,
0676             "clamping sdma_phase_quantum to %uK clock cycles\n",
0677                   value << unit);
0678         }
0679         phase_quantum =
0680             value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
0681             unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
0682     }
0683 
0684     for (i = 0; i < adev->sdma.num_instances; i++) {
0685         if (!amdgpu_sriov_vf(adev)) {
0686             f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
0687             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0688                          AUTO_CTXSW_ENABLE, enable ? 1 : 0);
0689         }
0690 
0691         if (enable && amdgpu_sdma_phase_quantum) {
0692             WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
0693                    phase_quantum);
0694             WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
0695                    phase_quantum);
0696             WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
0697                    phase_quantum);
0698         }
0699         if (!amdgpu_sriov_vf(adev))
0700             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
0701     }
0702 
0703 }
0704 
0705 /**
0706  * sdma_v5_0_enable - stop the async dma engines
0707  *
0708  * @adev: amdgpu_device pointer
0709  * @enable: enable/disable the DMA MEs.
0710  *
0711  * Halt or unhalt the async dma engines (NAVI10).
0712  */
0713 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
0714 {
0715     u32 f32_cntl;
0716     int i;
0717 
0718     if (!enable) {
0719         sdma_v5_0_gfx_stop(adev);
0720         sdma_v5_0_rlc_stop(adev);
0721     }
0722 
0723     if (amdgpu_sriov_vf(adev))
0724         return;
0725 
0726     for (i = 0; i < adev->sdma.num_instances; i++) {
0727         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
0728         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
0729         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
0730     }
0731 }
0732 
0733 /**
0734  * sdma_v5_0_gfx_resume - setup and start the async dma engines
0735  *
0736  * @adev: amdgpu_device pointer
0737  *
0738  * Set up the gfx DMA ring buffers and enable them (NAVI10).
0739  * Returns 0 for success, error for failure.
0740  */
0741 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
0742 {
0743     struct amdgpu_ring *ring;
0744     u32 rb_cntl, ib_cntl;
0745     u32 rb_bufsz;
0746     u32 doorbell;
0747     u32 doorbell_offset;
0748     u32 temp;
0749     u32 wptr_poll_cntl;
0750     u64 wptr_gpu_addr;
0751     int i, r;
0752 
0753     for (i = 0; i < adev->sdma.num_instances; i++) {
0754         ring = &adev->sdma.instance[i].ring;
0755 
0756         if (!amdgpu_sriov_vf(adev))
0757             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
0758 
0759         /* Set ring buffer size in dwords */
0760         rb_bufsz = order_base_2(ring->ring_size / 4);
0761         rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
0762         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
0763 #ifdef __BIG_ENDIAN
0764         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
0765         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
0766                     RPTR_WRITEBACK_SWAP_ENABLE, 1);
0767 #endif
0768         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
0769 
0770         /* Initialize the ring buffer's read and write pointers */
0771         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
0772         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
0773         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
0774         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
0775 
0776         /* setup the wptr shadow polling */
0777         wptr_gpu_addr = ring->wptr_gpu_addr;
0778         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
0779                lower_32_bits(wptr_gpu_addr));
0780         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
0781                upper_32_bits(wptr_gpu_addr));
0782         wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
0783                              mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
0784         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
0785                            SDMA0_GFX_RB_WPTR_POLL_CNTL,
0786                            F32_POLL_ENABLE, 1);
0787         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
0788                wptr_poll_cntl);
0789 
0790         /* set the wb address whether it's enabled or not */
0791         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
0792                upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
0793         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
0794                lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
0795 
0796         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
0797 
0798         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
0799                ring->gpu_addr >> 8);
0800         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
0801                ring->gpu_addr >> 40);
0802 
0803         ring->wptr = 0;
0804 
0805         /* before programing wptr to a less value, need set minor_ptr_update first */
0806         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
0807 
0808         if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
0809             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
0810                    lower_32_bits(ring->wptr << 2));
0811             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
0812                    upper_32_bits(ring->wptr << 2));
0813         }
0814 
0815         doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
0816         doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
0817                         mmSDMA0_GFX_DOORBELL_OFFSET));
0818 
0819         if (ring->use_doorbell) {
0820             doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
0821             doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
0822                     OFFSET, ring->doorbell_index);
0823         } else {
0824             doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
0825         }
0826         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
0827         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
0828                doorbell_offset);
0829 
0830         adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
0831                               ring->doorbell_index, 20);
0832 
0833         if (amdgpu_sriov_vf(adev))
0834             sdma_v5_0_ring_set_wptr(ring);
0835 
0836         /* set minor_ptr_update to 0 after wptr programed */
0837         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
0838 
0839         if (!amdgpu_sriov_vf(adev)) {
0840             /* set utc l1 enable flag always to 1 */
0841             temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
0842             temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
0843 
0844             /* enable MCBP */
0845             temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
0846             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
0847 
0848             /* Set up RESP_MODE to non-copy addresses */
0849             temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
0850             temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
0851             temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
0852             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
0853 
0854             /* program default cache read and write policy */
0855             temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
0856             /* clean read policy and write policy bits */
0857             temp &= 0xFF0FFF;
0858             temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
0859             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
0860         }
0861 
0862         if (!amdgpu_sriov_vf(adev)) {
0863             /* unhalt engine */
0864             temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
0865             temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
0866             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
0867         }
0868 
0869         /* enable DMA RB */
0870         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
0871         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
0872 
0873         ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
0874         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
0875 #ifdef __BIG_ENDIAN
0876         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
0877 #endif
0878         /* enable DMA IBs */
0879         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
0880 
0881         ring->sched.ready = true;
0882 
0883         if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
0884             sdma_v5_0_ctx_switch_enable(adev, true);
0885             sdma_v5_0_enable(adev, true);
0886         }
0887 
0888         r = amdgpu_ring_test_helper(ring);
0889         if (r)
0890             return r;
0891 
0892         if (adev->mman.buffer_funcs_ring == ring)
0893             amdgpu_ttm_set_buffer_funcs_status(adev, true);
0894     }
0895 
0896     return 0;
0897 }
0898 
0899 /**
0900  * sdma_v5_0_rlc_resume - setup and start the async dma engines
0901  *
0902  * @adev: amdgpu_device pointer
0903  *
0904  * Set up the compute DMA queues and enable them (NAVI10).
0905  * Returns 0 for success, error for failure.
0906  */
0907 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
0908 {
0909     return 0;
0910 }
0911 
0912 /**
0913  * sdma_v5_0_load_microcode - load the sDMA ME ucode
0914  *
0915  * @adev: amdgpu_device pointer
0916  *
0917  * Loads the sDMA0/1 ucode.
0918  * Returns 0 for success, -EINVAL if the ucode is not available.
0919  */
0920 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
0921 {
0922     const struct sdma_firmware_header_v1_0 *hdr;
0923     const __le32 *fw_data;
0924     u32 fw_size;
0925     int i, j;
0926 
0927     /* halt the MEs */
0928     sdma_v5_0_enable(adev, false);
0929 
0930     for (i = 0; i < adev->sdma.num_instances; i++) {
0931         if (!adev->sdma.instance[i].fw)
0932             return -EINVAL;
0933 
0934         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
0935         amdgpu_ucode_print_sdma_hdr(&hdr->header);
0936         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
0937 
0938         fw_data = (const __le32 *)
0939             (adev->sdma.instance[i].fw->data +
0940                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
0941 
0942         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
0943 
0944         for (j = 0; j < fw_size; j++) {
0945             if (amdgpu_emu_mode == 1 && j % 500 == 0)
0946                 msleep(1);
0947             WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
0948         }
0949 
0950         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
0951     }
0952 
0953     return 0;
0954 }
0955 
0956 /**
0957  * sdma_v5_0_start - setup and start the async dma engines
0958  *
0959  * @adev: amdgpu_device pointer
0960  *
0961  * Set up the DMA engines and enable them (NAVI10).
0962  * Returns 0 for success, error for failure.
0963  */
0964 static int sdma_v5_0_start(struct amdgpu_device *adev)
0965 {
0966     int r = 0;
0967 
0968     if (amdgpu_sriov_vf(adev)) {
0969         sdma_v5_0_ctx_switch_enable(adev, false);
0970         sdma_v5_0_enable(adev, false);
0971 
0972         /* set RB registers */
0973         r = sdma_v5_0_gfx_resume(adev);
0974         return r;
0975     }
0976 
0977     if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
0978         r = sdma_v5_0_load_microcode(adev);
0979         if (r)
0980             return r;
0981     }
0982 
0983     /* unhalt the MEs */
0984     sdma_v5_0_enable(adev, true);
0985     /* enable sdma ring preemption */
0986     sdma_v5_0_ctx_switch_enable(adev, true);
0987 
0988     /* start the gfx rings and rlc compute queues */
0989     r = sdma_v5_0_gfx_resume(adev);
0990     if (r)
0991         return r;
0992     r = sdma_v5_0_rlc_resume(adev);
0993 
0994     return r;
0995 }
0996 
0997 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
0998                   struct amdgpu_mqd_prop *prop)
0999 {
1000     struct v10_sdma_mqd *m = mqd;
1001     uint64_t wb_gpu_addr;
1002 
1003     m->sdmax_rlcx_rb_cntl =
1004         order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
1005         1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
1006         6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
1007         1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
1008 
1009     m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
1010     m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
1011 
1012     m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
1013                           mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
1014 
1015     wb_gpu_addr = prop->wptr_gpu_addr;
1016     m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
1017     m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
1018 
1019     wb_gpu_addr = prop->rptr_gpu_addr;
1020     m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
1021     m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
1022 
1023     m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
1024                             mmSDMA0_GFX_IB_CNTL));
1025 
1026     m->sdmax_rlcx_doorbell_offset =
1027         prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
1028 
1029     m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
1030 
1031     return 0;
1032 }
1033 
1034 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
1035 {
1036     adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
1037     adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
1038 }
1039 
1040 /**
1041  * sdma_v5_0_ring_test_ring - simple async dma engine test
1042  *
1043  * @ring: amdgpu_ring structure holding ring information
1044  *
1045  * Test the DMA engine by writing using it to write an
1046  * value to memory. (NAVI10).
1047  * Returns 0 for success, error for failure.
1048  */
1049 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
1050 {
1051     struct amdgpu_device *adev = ring->adev;
1052     unsigned i;
1053     unsigned index;
1054     int r;
1055     u32 tmp;
1056     u64 gpu_addr;
1057     volatile uint32_t *cpu_ptr = NULL;
1058 
1059     tmp = 0xCAFEDEAD;
1060 
1061     if (ring->is_mes_queue) {
1062         uint32_t offset = 0;
1063         offset = amdgpu_mes_ctx_get_offs(ring,
1064                      AMDGPU_MES_CTX_PADDING_OFFS);
1065         gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1066         cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1067         *cpu_ptr = tmp;
1068     } else {
1069         r = amdgpu_device_wb_get(adev, &index);
1070         if (r) {
1071             dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1072             return r;
1073         }
1074 
1075         gpu_addr = adev->wb.gpu_addr + (index * 4);
1076         adev->wb.wb[index] = cpu_to_le32(tmp);
1077     }
1078 
1079     r = amdgpu_ring_alloc(ring, 20);
1080     if (r) {
1081         DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1082         amdgpu_device_wb_free(adev, index);
1083         return r;
1084     }
1085 
1086     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1087               SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1088     amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1089     amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1090     amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1091     amdgpu_ring_write(ring, 0xDEADBEEF);
1092     amdgpu_ring_commit(ring);
1093 
1094     for (i = 0; i < adev->usec_timeout; i++) {
1095         if (ring->is_mes_queue)
1096             tmp = le32_to_cpu(*cpu_ptr);
1097         else
1098             tmp = le32_to_cpu(adev->wb.wb[index]);
1099         if (tmp == 0xDEADBEEF)
1100             break;
1101         if (amdgpu_emu_mode == 1)
1102             msleep(1);
1103         else
1104             udelay(1);
1105     }
1106 
1107     if (i >= adev->usec_timeout)
1108         r = -ETIMEDOUT;
1109 
1110     if (!ring->is_mes_queue)
1111         amdgpu_device_wb_free(adev, index);
1112 
1113     return r;
1114 }
1115 
1116 /**
1117  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1118  *
1119  * @ring: amdgpu_ring structure holding ring information
1120  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1121  *
1122  * Test a simple IB in the DMA ring (NAVI10).
1123  * Returns 0 on success, error on failure.
1124  */
1125 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1126 {
1127     struct amdgpu_device *adev = ring->adev;
1128     struct amdgpu_ib ib;
1129     struct dma_fence *f = NULL;
1130     unsigned index;
1131     long r;
1132     u32 tmp = 0;
1133     u64 gpu_addr;
1134     volatile uint32_t *cpu_ptr = NULL;
1135 
1136     tmp = 0xCAFEDEAD;
1137     memset(&ib, 0, sizeof(ib));
1138 
1139     if (ring->is_mes_queue) {
1140         uint32_t offset = 0;
1141         offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1142         ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1143         ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1144 
1145         offset = amdgpu_mes_ctx_get_offs(ring,
1146                      AMDGPU_MES_CTX_PADDING_OFFS);
1147         gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1148         cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1149         *cpu_ptr = tmp;
1150     } else {
1151         r = amdgpu_device_wb_get(adev, &index);
1152         if (r) {
1153             dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1154             return r;
1155         }
1156 
1157         gpu_addr = adev->wb.gpu_addr + (index * 4);
1158         adev->wb.wb[index] = cpu_to_le32(tmp);
1159 
1160         r = amdgpu_ib_get(adev, NULL, 256,
1161                     AMDGPU_IB_POOL_DIRECT, &ib);
1162         if (r) {
1163             DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1164             goto err0;
1165         }
1166     }
1167 
1168     ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1169         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1170     ib.ptr[1] = lower_32_bits(gpu_addr);
1171     ib.ptr[2] = upper_32_bits(gpu_addr);
1172     ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1173     ib.ptr[4] = 0xDEADBEEF;
1174     ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1175     ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1176     ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1177     ib.length_dw = 8;
1178 
1179     r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1180     if (r)
1181         goto err1;
1182 
1183     r = dma_fence_wait_timeout(f, false, timeout);
1184     if (r == 0) {
1185         DRM_ERROR("amdgpu: IB test timed out\n");
1186         r = -ETIMEDOUT;
1187         goto err1;
1188     } else if (r < 0) {
1189         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1190         goto err1;
1191     }
1192 
1193     if (ring->is_mes_queue)
1194         tmp = le32_to_cpu(*cpu_ptr);
1195     else
1196         tmp = le32_to_cpu(adev->wb.wb[index]);
1197 
1198     if (tmp == 0xDEADBEEF)
1199         r = 0;
1200     else
1201         r = -EINVAL;
1202 
1203 err1:
1204     amdgpu_ib_free(adev, &ib, NULL);
1205     dma_fence_put(f);
1206 err0:
1207     if (!ring->is_mes_queue)
1208         amdgpu_device_wb_free(adev, index);
1209     return r;
1210 }
1211 
1212 
1213 /**
1214  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1215  *
1216  * @ib: indirect buffer to fill with commands
1217  * @pe: addr of the page entry
1218  * @src: src addr to copy from
1219  * @count: number of page entries to update
1220  *
1221  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1222  */
1223 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1224                   uint64_t pe, uint64_t src,
1225                   unsigned count)
1226 {
1227     unsigned bytes = count * 8;
1228 
1229     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1230         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1231     ib->ptr[ib->length_dw++] = bytes - 1;
1232     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1233     ib->ptr[ib->length_dw++] = lower_32_bits(src);
1234     ib->ptr[ib->length_dw++] = upper_32_bits(src);
1235     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1236     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1237 
1238 }
1239 
1240 /**
1241  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1242  *
1243  * @ib: indirect buffer to fill with commands
1244  * @pe: addr of the page entry
1245  * @value: dst addr to write into pe
1246  * @count: number of page entries to update
1247  * @incr: increase next addr by incr bytes
1248  *
1249  * Update PTEs by writing them manually using sDMA (NAVI10).
1250  */
1251 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1252                    uint64_t value, unsigned count,
1253                    uint32_t incr)
1254 {
1255     unsigned ndw = count * 2;
1256 
1257     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1258         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1259     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1260     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1261     ib->ptr[ib->length_dw++] = ndw - 1;
1262     for (; ndw > 0; ndw -= 2) {
1263         ib->ptr[ib->length_dw++] = lower_32_bits(value);
1264         ib->ptr[ib->length_dw++] = upper_32_bits(value);
1265         value += incr;
1266     }
1267 }
1268 
1269 /**
1270  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1271  *
1272  * @ib: indirect buffer to fill with commands
1273  * @pe: addr of the page entry
1274  * @addr: dst addr to write into pe
1275  * @count: number of page entries to update
1276  * @incr: increase next addr by incr bytes
1277  * @flags: access flags
1278  *
1279  * Update the page tables using sDMA (NAVI10).
1280  */
1281 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1282                      uint64_t pe,
1283                      uint64_t addr, unsigned count,
1284                      uint32_t incr, uint64_t flags)
1285 {
1286     /* for physically contiguous pages (vram) */
1287     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1288     ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1289     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1290     ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1291     ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1292     ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1293     ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1294     ib->ptr[ib->length_dw++] = incr; /* increment size */
1295     ib->ptr[ib->length_dw++] = 0;
1296     ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1297 }
1298 
1299 /**
1300  * sdma_v5_0_ring_pad_ib - pad the IB
1301  * @ring: amdgpu_ring structure holding ring information
1302  * @ib: indirect buffer to fill with padding
1303  *
1304  * Pad the IB with NOPs to a boundary multiple of 8.
1305  */
1306 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1307 {
1308     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1309     u32 pad_count;
1310     int i;
1311 
1312     pad_count = (-ib->length_dw) & 0x7;
1313     for (i = 0; i < pad_count; i++)
1314         if (sdma && sdma->burst_nop && (i == 0))
1315             ib->ptr[ib->length_dw++] =
1316                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1317                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1318         else
1319             ib->ptr[ib->length_dw++] =
1320                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1321 }
1322 
1323 
1324 /**
1325  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1326  *
1327  * @ring: amdgpu_ring pointer
1328  *
1329  * Make sure all previous operations are completed (CIK).
1330  */
1331 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1332 {
1333     uint32_t seq = ring->fence_drv.sync_seq;
1334     uint64_t addr = ring->fence_drv.gpu_addr;
1335 
1336     /* wait for idle */
1337     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1338               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1339               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1340               SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1341     amdgpu_ring_write(ring, addr & 0xfffffffc);
1342     amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1343     amdgpu_ring_write(ring, seq); /* reference */
1344     amdgpu_ring_write(ring, 0xffffffff); /* mask */
1345     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1346               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1347 }
1348 
1349 
1350 /**
1351  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1352  *
1353  * @ring: amdgpu_ring pointer
1354  * @vmid: vmid number to use
1355  * @pd_addr: address
1356  *
1357  * Update the page table base and flush the VM TLB
1358  * using sDMA (NAVI10).
1359  */
1360 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1361                      unsigned vmid, uint64_t pd_addr)
1362 {
1363     amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1364 }
1365 
1366 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1367                      uint32_t reg, uint32_t val)
1368 {
1369     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1370               SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1371     amdgpu_ring_write(ring, reg);
1372     amdgpu_ring_write(ring, val);
1373 }
1374 
1375 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1376                      uint32_t val, uint32_t mask)
1377 {
1378     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1379               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1380               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1381     amdgpu_ring_write(ring, reg << 2);
1382     amdgpu_ring_write(ring, 0);
1383     amdgpu_ring_write(ring, val); /* reference */
1384     amdgpu_ring_write(ring, mask); /* mask */
1385     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1386               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1387 }
1388 
1389 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1390                            uint32_t reg0, uint32_t reg1,
1391                            uint32_t ref, uint32_t mask)
1392 {
1393     amdgpu_ring_emit_wreg(ring, reg0, ref);
1394     /* wait for a cycle to reset vm_inv_eng*_ack */
1395     amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1396     amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1397 }
1398 
1399 static int sdma_v5_0_early_init(void *handle)
1400 {
1401     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1402 
1403     sdma_v5_0_set_ring_funcs(adev);
1404     sdma_v5_0_set_buffer_funcs(adev);
1405     sdma_v5_0_set_vm_pte_funcs(adev);
1406     sdma_v5_0_set_irq_funcs(adev);
1407     sdma_v5_0_set_mqd_funcs(adev);
1408 
1409     return 0;
1410 }
1411 
1412 
1413 static int sdma_v5_0_sw_init(void *handle)
1414 {
1415     struct amdgpu_ring *ring;
1416     int r, i;
1417     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1418 
1419     /* SDMA trap event */
1420     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1421                   SDMA0_5_0__SRCID__SDMA_TRAP,
1422                   &adev->sdma.trap_irq);
1423     if (r)
1424         return r;
1425 
1426     /* SDMA trap event */
1427     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1428                   SDMA1_5_0__SRCID__SDMA_TRAP,
1429                   &adev->sdma.trap_irq);
1430     if (r)
1431         return r;
1432 
1433     r = sdma_v5_0_init_microcode(adev);
1434     if (r) {
1435         DRM_ERROR("Failed to load sdma firmware!\n");
1436         return r;
1437     }
1438 
1439     for (i = 0; i < adev->sdma.num_instances; i++) {
1440         ring = &adev->sdma.instance[i].ring;
1441         ring->ring_obj = NULL;
1442         ring->use_doorbell = true;
1443 
1444         DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1445                 ring->use_doorbell?"true":"false");
1446 
1447         ring->doorbell_index = (i == 0) ?
1448             (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1449             : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1450 
1451         sprintf(ring->name, "sdma%d", i);
1452         r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1453                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1454                      AMDGPU_SDMA_IRQ_INSTANCE1,
1455                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1456         if (r)
1457             return r;
1458     }
1459 
1460     return r;
1461 }
1462 
1463 static int sdma_v5_0_sw_fini(void *handle)
1464 {
1465     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1466     int i;
1467 
1468     for (i = 0; i < adev->sdma.num_instances; i++) {
1469         release_firmware(adev->sdma.instance[i].fw);
1470         adev->sdma.instance[i].fw = NULL;
1471 
1472         amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1473     }
1474 
1475     return 0;
1476 }
1477 
1478 static int sdma_v5_0_hw_init(void *handle)
1479 {
1480     int r;
1481     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1482 
1483     sdma_v5_0_init_golden_registers(adev);
1484 
1485     r = sdma_v5_0_start(adev);
1486 
1487     return r;
1488 }
1489 
1490 static int sdma_v5_0_hw_fini(void *handle)
1491 {
1492     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1493 
1494     if (amdgpu_sriov_vf(adev))
1495         return 0;
1496 
1497     sdma_v5_0_ctx_switch_enable(adev, false);
1498     sdma_v5_0_enable(adev, false);
1499 
1500     return 0;
1501 }
1502 
1503 static int sdma_v5_0_suspend(void *handle)
1504 {
1505     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1506 
1507     return sdma_v5_0_hw_fini(adev);
1508 }
1509 
1510 static int sdma_v5_0_resume(void *handle)
1511 {
1512     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1513 
1514     return sdma_v5_0_hw_init(adev);
1515 }
1516 
1517 static bool sdma_v5_0_is_idle(void *handle)
1518 {
1519     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1520     u32 i;
1521 
1522     for (i = 0; i < adev->sdma.num_instances; i++) {
1523         u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1524 
1525         if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1526             return false;
1527     }
1528 
1529     return true;
1530 }
1531 
1532 static int sdma_v5_0_wait_for_idle(void *handle)
1533 {
1534     unsigned i;
1535     u32 sdma0, sdma1;
1536     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1537 
1538     for (i = 0; i < adev->usec_timeout; i++) {
1539         sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1540         sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1541 
1542         if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1543             return 0;
1544         udelay(1);
1545     }
1546     return -ETIMEDOUT;
1547 }
1548 
1549 static int sdma_v5_0_soft_reset(void *handle)
1550 {
1551     /* todo */
1552 
1553     return 0;
1554 }
1555 
1556 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1557 {
1558     int i, r = 0;
1559     struct amdgpu_device *adev = ring->adev;
1560     u32 index = 0;
1561     u64 sdma_gfx_preempt;
1562 
1563     amdgpu_sdma_get_index_from_ring(ring, &index);
1564     if (index == 0)
1565         sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1566     else
1567         sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1568 
1569     /* assert preemption condition */
1570     amdgpu_ring_set_preempt_cond_exec(ring, false);
1571 
1572     /* emit the trailing fence */
1573     ring->trail_seq += 1;
1574     amdgpu_ring_alloc(ring, 10);
1575     sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1576                   ring->trail_seq, 0);
1577     amdgpu_ring_commit(ring);
1578 
1579     /* assert IB preemption */
1580     WREG32(sdma_gfx_preempt, 1);
1581 
1582     /* poll the trailing fence */
1583     for (i = 0; i < adev->usec_timeout; i++) {
1584         if (ring->trail_seq ==
1585             le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1586             break;
1587         udelay(1);
1588     }
1589 
1590     if (i >= adev->usec_timeout) {
1591         r = -EINVAL;
1592         DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1593     }
1594 
1595     /* deassert IB preemption */
1596     WREG32(sdma_gfx_preempt, 0);
1597 
1598     /* deassert the preemption condition */
1599     amdgpu_ring_set_preempt_cond_exec(ring, true);
1600     return r;
1601 }
1602 
1603 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1604                     struct amdgpu_irq_src *source,
1605                     unsigned type,
1606                     enum amdgpu_interrupt_state state)
1607 {
1608     u32 sdma_cntl;
1609 
1610     if (!amdgpu_sriov_vf(adev)) {
1611         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1612             sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1613             sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1614 
1615         sdma_cntl = RREG32(reg_offset);
1616         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1617                       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1618         WREG32(reg_offset, sdma_cntl);
1619     }
1620 
1621     return 0;
1622 }
1623 
1624 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1625                       struct amdgpu_irq_src *source,
1626                       struct amdgpu_iv_entry *entry)
1627 {
1628     uint32_t mes_queue_id = entry->src_data[0];
1629 
1630     DRM_DEBUG("IH: SDMA trap\n");
1631 
1632     if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1633         struct amdgpu_mes_queue *queue;
1634 
1635         mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1636 
1637         spin_lock(&adev->mes.queue_id_lock);
1638         queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1639         if (queue) {
1640             DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1641             amdgpu_fence_process(queue->ring);
1642         }
1643         spin_unlock(&adev->mes.queue_id_lock);
1644         return 0;
1645     }
1646 
1647     switch (entry->client_id) {
1648     case SOC15_IH_CLIENTID_SDMA0:
1649         switch (entry->ring_id) {
1650         case 0:
1651             amdgpu_fence_process(&adev->sdma.instance[0].ring);
1652             break;
1653         case 1:
1654             /* XXX compute */
1655             break;
1656         case 2:
1657             /* XXX compute */
1658             break;
1659         case 3:
1660             /* XXX page queue*/
1661             break;
1662         }
1663         break;
1664     case SOC15_IH_CLIENTID_SDMA1:
1665         switch (entry->ring_id) {
1666         case 0:
1667             amdgpu_fence_process(&adev->sdma.instance[1].ring);
1668             break;
1669         case 1:
1670             /* XXX compute */
1671             break;
1672         case 2:
1673             /* XXX compute */
1674             break;
1675         case 3:
1676             /* XXX page queue*/
1677             break;
1678         }
1679         break;
1680     }
1681     return 0;
1682 }
1683 
1684 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1685                           struct amdgpu_irq_src *source,
1686                           struct amdgpu_iv_entry *entry)
1687 {
1688     return 0;
1689 }
1690 
1691 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1692                                bool enable)
1693 {
1694     uint32_t data, def;
1695     int i;
1696 
1697     for (i = 0; i < adev->sdma.num_instances; i++) {
1698         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1699             /* Enable sdma clock gating */
1700             def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1701             data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1702                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1703                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1704                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1705                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1706                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1707                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1708                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1709             if (def != data)
1710                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1711         } else {
1712             /* Disable sdma clock gating */
1713             def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1714             data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1715                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1716                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1717                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1718                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1719                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1720                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1721                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1722             if (def != data)
1723                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1724         }
1725     }
1726 }
1727 
1728 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1729                               bool enable)
1730 {
1731     uint32_t data, def;
1732     int i;
1733 
1734     for (i = 0; i < adev->sdma.num_instances; i++) {
1735         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1736             /* Enable sdma mem light sleep */
1737             def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1738             data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1739             if (def != data)
1740                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1741 
1742         } else {
1743             /* Disable sdma mem light sleep */
1744             def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1745             data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1746             if (def != data)
1747                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1748 
1749         }
1750     }
1751 }
1752 
1753 static int sdma_v5_0_set_clockgating_state(void *handle,
1754                        enum amd_clockgating_state state)
1755 {
1756     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1757 
1758     if (amdgpu_sriov_vf(adev))
1759         return 0;
1760 
1761     switch (adev->ip_versions[SDMA0_HWIP][0]) {
1762     case IP_VERSION(5, 0, 0):
1763     case IP_VERSION(5, 0, 2):
1764     case IP_VERSION(5, 0, 5):
1765         sdma_v5_0_update_medium_grain_clock_gating(adev,
1766                 state == AMD_CG_STATE_GATE);
1767         sdma_v5_0_update_medium_grain_light_sleep(adev,
1768                 state == AMD_CG_STATE_GATE);
1769         break;
1770     default:
1771         break;
1772     }
1773 
1774     return 0;
1775 }
1776 
1777 static int sdma_v5_0_set_powergating_state(void *handle,
1778                       enum amd_powergating_state state)
1779 {
1780     return 0;
1781 }
1782 
1783 static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1784 {
1785     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1786     int data;
1787 
1788     if (amdgpu_sriov_vf(adev))
1789         *flags = 0;
1790 
1791     /* AMD_CG_SUPPORT_SDMA_MGCG */
1792     data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1793     if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1794         *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1795 
1796     /* AMD_CG_SUPPORT_SDMA_LS */
1797     data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1798     if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1799         *flags |= AMD_CG_SUPPORT_SDMA_LS;
1800 }
1801 
1802 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1803     .name = "sdma_v5_0",
1804     .early_init = sdma_v5_0_early_init,
1805     .late_init = NULL,
1806     .sw_init = sdma_v5_0_sw_init,
1807     .sw_fini = sdma_v5_0_sw_fini,
1808     .hw_init = sdma_v5_0_hw_init,
1809     .hw_fini = sdma_v5_0_hw_fini,
1810     .suspend = sdma_v5_0_suspend,
1811     .resume = sdma_v5_0_resume,
1812     .is_idle = sdma_v5_0_is_idle,
1813     .wait_for_idle = sdma_v5_0_wait_for_idle,
1814     .soft_reset = sdma_v5_0_soft_reset,
1815     .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1816     .set_powergating_state = sdma_v5_0_set_powergating_state,
1817     .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1818 };
1819 
1820 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1821     .type = AMDGPU_RING_TYPE_SDMA,
1822     .align_mask = 0xf,
1823     .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1824     .support_64bit_ptrs = true,
1825     .secure_submission_supported = true,
1826     .vmhub = AMDGPU_GFXHUB_0,
1827     .get_rptr = sdma_v5_0_ring_get_rptr,
1828     .get_wptr = sdma_v5_0_ring_get_wptr,
1829     .set_wptr = sdma_v5_0_ring_set_wptr,
1830     .emit_frame_size =
1831         5 + /* sdma_v5_0_ring_init_cond_exec */
1832         6 + /* sdma_v5_0_ring_emit_hdp_flush */
1833         3 + /* hdp_invalidate */
1834         6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1835         /* sdma_v5_0_ring_emit_vm_flush */
1836         SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1837         SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1838         10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1839     .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1840     .emit_ib = sdma_v5_0_ring_emit_ib,
1841     .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1842     .emit_fence = sdma_v5_0_ring_emit_fence,
1843     .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1844     .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1845     .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1846     .test_ring = sdma_v5_0_ring_test_ring,
1847     .test_ib = sdma_v5_0_ring_test_ib,
1848     .insert_nop = sdma_v5_0_ring_insert_nop,
1849     .pad_ib = sdma_v5_0_ring_pad_ib,
1850     .emit_wreg = sdma_v5_0_ring_emit_wreg,
1851     .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1852     .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1853     .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1854     .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1855     .preempt_ib = sdma_v5_0_ring_preempt_ib,
1856 };
1857 
1858 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1859 {
1860     int i;
1861 
1862     for (i = 0; i < adev->sdma.num_instances; i++) {
1863         adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1864         adev->sdma.instance[i].ring.me = i;
1865     }
1866 }
1867 
1868 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1869     .set = sdma_v5_0_set_trap_irq_state,
1870     .process = sdma_v5_0_process_trap_irq,
1871 };
1872 
1873 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1874     .process = sdma_v5_0_process_illegal_inst_irq,
1875 };
1876 
1877 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1878 {
1879     adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1880                     adev->sdma.num_instances;
1881     adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1882     adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1883 }
1884 
1885 /**
1886  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1887  *
1888  * @ib: indirect buffer to copy to
1889  * @src_offset: src GPU address
1890  * @dst_offset: dst GPU address
1891  * @byte_count: number of bytes to xfer
1892  * @tmz: if a secure copy should be used
1893  *
1894  * Copy GPU buffers using the DMA engine (NAVI10).
1895  * Used by the amdgpu ttm implementation to move pages if
1896  * registered as the asic copy callback.
1897  */
1898 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1899                        uint64_t src_offset,
1900                        uint64_t dst_offset,
1901                        uint32_t byte_count,
1902                        bool tmz)
1903 {
1904     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1905         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1906         SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1907     ib->ptr[ib->length_dw++] = byte_count - 1;
1908     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1909     ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1910     ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1911     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1912     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1913 }
1914 
1915 /**
1916  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1917  *
1918  * @ib: indirect buffer to fill
1919  * @src_data: value to write to buffer
1920  * @dst_offset: dst GPU address
1921  * @byte_count: number of bytes to xfer
1922  *
1923  * Fill GPU buffers using the DMA engine (NAVI10).
1924  */
1925 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1926                        uint32_t src_data,
1927                        uint64_t dst_offset,
1928                        uint32_t byte_count)
1929 {
1930     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1931     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1932     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1933     ib->ptr[ib->length_dw++] = src_data;
1934     ib->ptr[ib->length_dw++] = byte_count - 1;
1935 }
1936 
1937 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1938     .copy_max_bytes = 0x400000,
1939     .copy_num_dw = 7,
1940     .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1941 
1942     .fill_max_bytes = 0x400000,
1943     .fill_num_dw = 5,
1944     .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1945 };
1946 
1947 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1948 {
1949     if (adev->mman.buffer_funcs == NULL) {
1950         adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1951         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1952     }
1953 }
1954 
1955 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1956     .copy_pte_num_dw = 7,
1957     .copy_pte = sdma_v5_0_vm_copy_pte,
1958     .write_pte = sdma_v5_0_vm_write_pte,
1959     .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1960 };
1961 
1962 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1963 {
1964     unsigned i;
1965 
1966     if (adev->vm_manager.vm_pte_funcs == NULL) {
1967         adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1968         for (i = 0; i < adev->sdma.num_instances; i++) {
1969             adev->vm_manager.vm_pte_scheds[i] =
1970                 &adev->sdma.instance[i].ring.sched;
1971         }
1972         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1973     }
1974 }
1975 
1976 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1977     .type = AMD_IP_BLOCK_TYPE_SDMA,
1978     .major = 5,
1979     .minor = 0,
1980     .rev = 0,
1981     .funcs = &sdma_v5_0_ip_funcs,
1982 };
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