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0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024 
0025 #include <linux/delay.h>
0026 #include <linux/firmware.h>
0027 #include <linux/module.h>
0028 
0029 #include "amdgpu.h"
0030 #include "amdgpu_ucode.h"
0031 #include "amdgpu_trace.h"
0032 #include "vi.h"
0033 #include "vid.h"
0034 
0035 #include "oss/oss_3_0_d.h"
0036 #include "oss/oss_3_0_sh_mask.h"
0037 
0038 #include "gmc/gmc_8_1_d.h"
0039 #include "gmc/gmc_8_1_sh_mask.h"
0040 
0041 #include "gca/gfx_8_0_d.h"
0042 #include "gca/gfx_8_0_enum.h"
0043 #include "gca/gfx_8_0_sh_mask.h"
0044 
0045 #include "bif/bif_5_0_d.h"
0046 #include "bif/bif_5_0_sh_mask.h"
0047 
0048 #include "tonga_sdma_pkt_open.h"
0049 
0050 #include "ivsrcid/ivsrcid_vislands30.h"
0051 
0052 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
0053 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
0054 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
0055 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
0056 
0057 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
0058 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
0059 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
0060 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
0061 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
0062 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
0063 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
0064 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
0065 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
0066 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
0067 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
0068 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
0069 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
0070 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
0071 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
0072 
0073 
0074 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
0075 {
0076     SDMA0_REGISTER_OFFSET,
0077     SDMA1_REGISTER_OFFSET
0078 };
0079 
0080 static const u32 golden_settings_tonga_a11[] =
0081 {
0082     mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
0083     mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
0084     mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0085     mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0086     mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0087     mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
0088     mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
0089     mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0090     mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0091     mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0092 };
0093 
0094 static const u32 tonga_mgcg_cgcg_init[] =
0095 {
0096     mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
0097     mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
0098 };
0099 
0100 static const u32 golden_settings_fiji_a10[] =
0101 {
0102     mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
0103     mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0104     mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0105     mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0106     mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
0107     mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0108     mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0109     mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0110 };
0111 
0112 static const u32 fiji_mgcg_cgcg_init[] =
0113 {
0114     mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
0115     mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
0116 };
0117 
0118 static const u32 golden_settings_polaris11_a11[] =
0119 {
0120     mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
0121     mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
0122     mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0123     mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0124     mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0125     mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
0126     mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
0127     mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0128     mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0129     mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0130 };
0131 
0132 static const u32 golden_settings_polaris10_a11[] =
0133 {
0134     mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
0135     mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
0136     mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0137     mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0138     mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0139     mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
0140     mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
0141     mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
0142     mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
0143     mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
0144 };
0145 
0146 static const u32 cz_golden_settings_a11[] =
0147 {
0148     mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
0149     mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
0150     mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
0151     mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
0152     mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
0153     mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
0154     mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
0155     mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
0156     mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
0157     mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
0158     mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
0159     mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
0160 };
0161 
0162 static const u32 cz_mgcg_cgcg_init[] =
0163 {
0164     mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
0165     mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
0166 };
0167 
0168 static const u32 stoney_golden_settings_a11[] =
0169 {
0170     mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
0171     mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
0172     mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
0173     mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
0174 };
0175 
0176 static const u32 stoney_mgcg_cgcg_init[] =
0177 {
0178     mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
0179 };
0180 
0181 /*
0182  * sDMA - System DMA
0183  * Starting with CIK, the GPU has new asynchronous
0184  * DMA engines.  These engines are used for compute
0185  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
0186  * and each one supports 1 ring buffer used for gfx
0187  * and 2 queues used for compute.
0188  *
0189  * The programming model is very similar to the CP
0190  * (ring buffer, IBs, etc.), but sDMA has it's own
0191  * packet format that is different from the PM4 format
0192  * used by the CP. sDMA supports copying data, writing
0193  * embedded data, solid fills, and a number of other
0194  * things.  It also has support for tiling/detiling of
0195  * buffers.
0196  */
0197 
0198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
0199 {
0200     switch (adev->asic_type) {
0201     case CHIP_FIJI:
0202         amdgpu_device_program_register_sequence(adev,
0203                             fiji_mgcg_cgcg_init,
0204                             ARRAY_SIZE(fiji_mgcg_cgcg_init));
0205         amdgpu_device_program_register_sequence(adev,
0206                             golden_settings_fiji_a10,
0207                             ARRAY_SIZE(golden_settings_fiji_a10));
0208         break;
0209     case CHIP_TONGA:
0210         amdgpu_device_program_register_sequence(adev,
0211                             tonga_mgcg_cgcg_init,
0212                             ARRAY_SIZE(tonga_mgcg_cgcg_init));
0213         amdgpu_device_program_register_sequence(adev,
0214                             golden_settings_tonga_a11,
0215                             ARRAY_SIZE(golden_settings_tonga_a11));
0216         break;
0217     case CHIP_POLARIS11:
0218     case CHIP_POLARIS12:
0219     case CHIP_VEGAM:
0220         amdgpu_device_program_register_sequence(adev,
0221                             golden_settings_polaris11_a11,
0222                             ARRAY_SIZE(golden_settings_polaris11_a11));
0223         break;
0224     case CHIP_POLARIS10:
0225         amdgpu_device_program_register_sequence(adev,
0226                             golden_settings_polaris10_a11,
0227                             ARRAY_SIZE(golden_settings_polaris10_a11));
0228         break;
0229     case CHIP_CARRIZO:
0230         amdgpu_device_program_register_sequence(adev,
0231                             cz_mgcg_cgcg_init,
0232                             ARRAY_SIZE(cz_mgcg_cgcg_init));
0233         amdgpu_device_program_register_sequence(adev,
0234                             cz_golden_settings_a11,
0235                             ARRAY_SIZE(cz_golden_settings_a11));
0236         break;
0237     case CHIP_STONEY:
0238         amdgpu_device_program_register_sequence(adev,
0239                             stoney_mgcg_cgcg_init,
0240                             ARRAY_SIZE(stoney_mgcg_cgcg_init));
0241         amdgpu_device_program_register_sequence(adev,
0242                             stoney_golden_settings_a11,
0243                             ARRAY_SIZE(stoney_golden_settings_a11));
0244         break;
0245     default:
0246         break;
0247     }
0248 }
0249 
0250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
0251 {
0252     int i;
0253     for (i = 0; i < adev->sdma.num_instances; i++) {
0254         release_firmware(adev->sdma.instance[i].fw);
0255         adev->sdma.instance[i].fw = NULL;
0256     }
0257 }
0258 
0259 /**
0260  * sdma_v3_0_init_microcode - load ucode images from disk
0261  *
0262  * @adev: amdgpu_device pointer
0263  *
0264  * Use the firmware interface to load the ucode images into
0265  * the driver (not loaded into hw).
0266  * Returns 0 on success, error on failure.
0267  */
0268 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
0269 {
0270     const char *chip_name;
0271     char fw_name[30];
0272     int err = 0, i;
0273     struct amdgpu_firmware_info *info = NULL;
0274     const struct common_firmware_header *header = NULL;
0275     const struct sdma_firmware_header_v1_0 *hdr;
0276 
0277     DRM_DEBUG("\n");
0278 
0279     switch (adev->asic_type) {
0280     case CHIP_TONGA:
0281         chip_name = "tonga";
0282         break;
0283     case CHIP_FIJI:
0284         chip_name = "fiji";
0285         break;
0286     case CHIP_POLARIS10:
0287         chip_name = "polaris10";
0288         break;
0289     case CHIP_POLARIS11:
0290         chip_name = "polaris11";
0291         break;
0292     case CHIP_POLARIS12:
0293         chip_name = "polaris12";
0294         break;
0295     case CHIP_VEGAM:
0296         chip_name = "vegam";
0297         break;
0298     case CHIP_CARRIZO:
0299         chip_name = "carrizo";
0300         break;
0301     case CHIP_STONEY:
0302         chip_name = "stoney";
0303         break;
0304     default: BUG();
0305     }
0306 
0307     for (i = 0; i < adev->sdma.num_instances; i++) {
0308         if (i == 0)
0309             snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
0310         else
0311             snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
0312         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
0313         if (err)
0314             goto out;
0315         err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
0316         if (err)
0317             goto out;
0318         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
0319         adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
0320         adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
0321         if (adev->sdma.instance[i].feature_version >= 20)
0322             adev->sdma.instance[i].burst_nop = true;
0323 
0324         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
0325         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
0326         info->fw = adev->sdma.instance[i].fw;
0327         header = (const struct common_firmware_header *)info->fw->data;
0328         adev->firmware.fw_size +=
0329             ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
0330 
0331     }
0332 out:
0333     if (err) {
0334         pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
0335         for (i = 0; i < adev->sdma.num_instances; i++) {
0336             release_firmware(adev->sdma.instance[i].fw);
0337             adev->sdma.instance[i].fw = NULL;
0338         }
0339     }
0340     return err;
0341 }
0342 
0343 /**
0344  * sdma_v3_0_ring_get_rptr - get the current read pointer
0345  *
0346  * @ring: amdgpu ring pointer
0347  *
0348  * Get the current rptr from the hardware (VI+).
0349  */
0350 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
0351 {
0352     /* XXX check if swapping is necessary on BE */
0353     return *ring->rptr_cpu_addr >> 2;
0354 }
0355 
0356 /**
0357  * sdma_v3_0_ring_get_wptr - get the current write pointer
0358  *
0359  * @ring: amdgpu ring pointer
0360  *
0361  * Get the current wptr from the hardware (VI+).
0362  */
0363 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
0364 {
0365     struct amdgpu_device *adev = ring->adev;
0366     u32 wptr;
0367 
0368     if (ring->use_doorbell || ring->use_pollmem) {
0369         /* XXX check if swapping is necessary on BE */
0370         wptr = *ring->wptr_cpu_addr >> 2;
0371     } else {
0372         wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
0373     }
0374 
0375     return wptr;
0376 }
0377 
0378 /**
0379  * sdma_v3_0_ring_set_wptr - commit the write pointer
0380  *
0381  * @ring: amdgpu ring pointer
0382  *
0383  * Write the wptr back to the hardware (VI+).
0384  */
0385 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
0386 {
0387     struct amdgpu_device *adev = ring->adev;
0388 
0389     if (ring->use_doorbell) {
0390         u32 *wb = (u32 *)ring->wptr_cpu_addr;
0391         /* XXX check if swapping is necessary on BE */
0392         WRITE_ONCE(*wb, ring->wptr << 2);
0393         WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
0394     } else if (ring->use_pollmem) {
0395         u32 *wb = (u32 *)ring->wptr_cpu_addr;
0396 
0397         WRITE_ONCE(*wb, ring->wptr << 2);
0398     } else {
0399         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
0400     }
0401 }
0402 
0403 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
0404 {
0405     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
0406     int i;
0407 
0408     for (i = 0; i < count; i++)
0409         if (sdma && sdma->burst_nop && (i == 0))
0410             amdgpu_ring_write(ring, ring->funcs->nop |
0411                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
0412         else
0413             amdgpu_ring_write(ring, ring->funcs->nop);
0414 }
0415 
0416 /**
0417  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
0418  *
0419  * @ring: amdgpu ring pointer
0420  * @job: job to retrieve vmid from
0421  * @ib: IB object to schedule
0422  * @flags: unused
0423  *
0424  * Schedule an IB in the DMA ring (VI).
0425  */
0426 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
0427                    struct amdgpu_job *job,
0428                    struct amdgpu_ib *ib,
0429                    uint32_t flags)
0430 {
0431     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
0432 
0433     /* IB packet must end on a 8 DW boundary */
0434     sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
0435 
0436     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
0437               SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
0438     /* base must be 32 byte aligned */
0439     amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
0440     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
0441     amdgpu_ring_write(ring, ib->length_dw);
0442     amdgpu_ring_write(ring, 0);
0443     amdgpu_ring_write(ring, 0);
0444 
0445 }
0446 
0447 /**
0448  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
0449  *
0450  * @ring: amdgpu ring pointer
0451  *
0452  * Emit an hdp flush packet on the requested DMA ring.
0453  */
0454 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
0455 {
0456     u32 ref_and_mask = 0;
0457 
0458     if (ring->me == 0)
0459         ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
0460     else
0461         ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
0462 
0463     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
0464               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
0465               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
0466     amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
0467     amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
0468     amdgpu_ring_write(ring, ref_and_mask); /* reference */
0469     amdgpu_ring_write(ring, ref_and_mask); /* mask */
0470     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
0471               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
0472 }
0473 
0474 /**
0475  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
0476  *
0477  * @ring: amdgpu ring pointer
0478  * @addr: address
0479  * @seq: sequence number
0480  * @flags: fence related flags
0481  *
0482  * Add a DMA fence packet to the ring to write
0483  * the fence seq number and DMA trap packet to generate
0484  * an interrupt if needed (VI).
0485  */
0486 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0487                       unsigned flags)
0488 {
0489     bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
0490     /* write the fence */
0491     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
0492     amdgpu_ring_write(ring, lower_32_bits(addr));
0493     amdgpu_ring_write(ring, upper_32_bits(addr));
0494     amdgpu_ring_write(ring, lower_32_bits(seq));
0495 
0496     /* optionally write high bits as well */
0497     if (write64bit) {
0498         addr += 4;
0499         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
0500         amdgpu_ring_write(ring, lower_32_bits(addr));
0501         amdgpu_ring_write(ring, upper_32_bits(addr));
0502         amdgpu_ring_write(ring, upper_32_bits(seq));
0503     }
0504 
0505     /* generate an interrupt */
0506     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
0507     amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
0508 }
0509 
0510 /**
0511  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
0512  *
0513  * @adev: amdgpu_device pointer
0514  *
0515  * Stop the gfx async dma ring buffers (VI).
0516  */
0517 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
0518 {
0519     struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
0520     struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
0521     u32 rb_cntl, ib_cntl;
0522     int i;
0523 
0524     if ((adev->mman.buffer_funcs_ring == sdma0) ||
0525         (adev->mman.buffer_funcs_ring == sdma1))
0526         amdgpu_ttm_set_buffer_funcs_status(adev, false);
0527 
0528     for (i = 0; i < adev->sdma.num_instances; i++) {
0529         rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
0530         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
0531         WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
0532         ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
0533         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
0534         WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
0535     }
0536 }
0537 
0538 /**
0539  * sdma_v3_0_rlc_stop - stop the compute async dma engines
0540  *
0541  * @adev: amdgpu_device pointer
0542  *
0543  * Stop the compute async dma queues (VI).
0544  */
0545 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
0546 {
0547     /* XXX todo */
0548 }
0549 
0550 /**
0551  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
0552  *
0553  * @adev: amdgpu_device pointer
0554  * @enable: enable/disable the DMA MEs context switch.
0555  *
0556  * Halt or unhalt the async dma engines context switch (VI).
0557  */
0558 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
0559 {
0560     u32 f32_cntl, phase_quantum = 0;
0561     int i;
0562 
0563     if (amdgpu_sdma_phase_quantum) {
0564         unsigned value = amdgpu_sdma_phase_quantum;
0565         unsigned unit = 0;
0566 
0567         while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0568                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
0569             value = (value + 1) >> 1;
0570             unit++;
0571         }
0572         if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0573                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
0574             value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0575                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
0576             unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0577                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
0578             WARN_ONCE(1,
0579             "clamping sdma_phase_quantum to %uK clock cycles\n",
0580                   value << unit);
0581         }
0582         phase_quantum =
0583             value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
0584             unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
0585     }
0586 
0587     for (i = 0; i < adev->sdma.num_instances; i++) {
0588         f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
0589         if (enable) {
0590             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0591                     AUTO_CTXSW_ENABLE, 1);
0592             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0593                     ATC_L1_ENABLE, 1);
0594             if (amdgpu_sdma_phase_quantum) {
0595                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
0596                        phase_quantum);
0597                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
0598                        phase_quantum);
0599             }
0600         } else {
0601             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0602                     AUTO_CTXSW_ENABLE, 0);
0603             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0604                     ATC_L1_ENABLE, 1);
0605         }
0606 
0607         WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
0608     }
0609 }
0610 
0611 /**
0612  * sdma_v3_0_enable - stop the async dma engines
0613  *
0614  * @adev: amdgpu_device pointer
0615  * @enable: enable/disable the DMA MEs.
0616  *
0617  * Halt or unhalt the async dma engines (VI).
0618  */
0619 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
0620 {
0621     u32 f32_cntl;
0622     int i;
0623 
0624     if (!enable) {
0625         sdma_v3_0_gfx_stop(adev);
0626         sdma_v3_0_rlc_stop(adev);
0627     }
0628 
0629     for (i = 0; i < adev->sdma.num_instances; i++) {
0630         f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
0631         if (enable)
0632             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
0633         else
0634             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
0635         WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
0636     }
0637 }
0638 
0639 /**
0640  * sdma_v3_0_gfx_resume - setup and start the async dma engines
0641  *
0642  * @adev: amdgpu_device pointer
0643  *
0644  * Set up the gfx DMA ring buffers and enable them (VI).
0645  * Returns 0 for success, error for failure.
0646  */
0647 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
0648 {
0649     struct amdgpu_ring *ring;
0650     u32 rb_cntl, ib_cntl, wptr_poll_cntl;
0651     u32 rb_bufsz;
0652     u32 doorbell;
0653     u64 wptr_gpu_addr;
0654     int i, j, r;
0655 
0656     for (i = 0; i < adev->sdma.num_instances; i++) {
0657         ring = &adev->sdma.instance[i].ring;
0658         amdgpu_ring_clear_ring(ring);
0659 
0660         mutex_lock(&adev->srbm_mutex);
0661         for (j = 0; j < 16; j++) {
0662             vi_srbm_select(adev, 0, 0, 0, j);
0663             /* SDMA GFX */
0664             WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
0665             WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
0666         }
0667         vi_srbm_select(adev, 0, 0, 0, 0);
0668         mutex_unlock(&adev->srbm_mutex);
0669 
0670         WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
0671                adev->gfx.config.gb_addr_config & 0x70);
0672 
0673         WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
0674 
0675         /* Set ring buffer size in dwords */
0676         rb_bufsz = order_base_2(ring->ring_size / 4);
0677         rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
0678         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
0679 #ifdef __BIG_ENDIAN
0680         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
0681         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
0682                     RPTR_WRITEBACK_SWAP_ENABLE, 1);
0683 #endif
0684         WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
0685 
0686         /* Initialize the ring buffer's read and write pointers */
0687         ring->wptr = 0;
0688         WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
0689         sdma_v3_0_ring_set_wptr(ring);
0690         WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
0691         WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
0692 
0693         /* set the wb address whether it's enabled or not */
0694         WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
0695                upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
0696         WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
0697                lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
0698 
0699         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
0700 
0701         WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
0702         WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
0703 
0704         doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
0705 
0706         if (ring->use_doorbell) {
0707             doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
0708                          OFFSET, ring->doorbell_index);
0709             doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
0710         } else {
0711             doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
0712         }
0713         WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
0714 
0715         /* setup the wptr shadow polling */
0716         wptr_gpu_addr = ring->wptr_gpu_addr;
0717 
0718         WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
0719                lower_32_bits(wptr_gpu_addr));
0720         WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
0721                upper_32_bits(wptr_gpu_addr));
0722         wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
0723         if (ring->use_pollmem) {
0724             /*wptr polling is not enogh fast, directly clean the wptr register */
0725             WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
0726             wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
0727                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
0728                                ENABLE, 1);
0729         } else {
0730             wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
0731                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
0732                                ENABLE, 0);
0733         }
0734         WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
0735 
0736         /* enable DMA RB */
0737         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
0738         WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
0739 
0740         ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
0741         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
0742 #ifdef __BIG_ENDIAN
0743         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
0744 #endif
0745         /* enable DMA IBs */
0746         WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
0747 
0748         ring->sched.ready = true;
0749     }
0750 
0751     /* unhalt the MEs */
0752     sdma_v3_0_enable(adev, true);
0753     /* enable sdma ring preemption */
0754     sdma_v3_0_ctx_switch_enable(adev, true);
0755 
0756     for (i = 0; i < adev->sdma.num_instances; i++) {
0757         ring = &adev->sdma.instance[i].ring;
0758         r = amdgpu_ring_test_helper(ring);
0759         if (r)
0760             return r;
0761 
0762         if (adev->mman.buffer_funcs_ring == ring)
0763             amdgpu_ttm_set_buffer_funcs_status(adev, true);
0764     }
0765 
0766     return 0;
0767 }
0768 
0769 /**
0770  * sdma_v3_0_rlc_resume - setup and start the async dma engines
0771  *
0772  * @adev: amdgpu_device pointer
0773  *
0774  * Set up the compute DMA queues and enable them (VI).
0775  * Returns 0 for success, error for failure.
0776  */
0777 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
0778 {
0779     /* XXX todo */
0780     return 0;
0781 }
0782 
0783 /**
0784  * sdma_v3_0_start - setup and start the async dma engines
0785  *
0786  * @adev: amdgpu_device pointer
0787  *
0788  * Set up the DMA engines and enable them (VI).
0789  * Returns 0 for success, error for failure.
0790  */
0791 static int sdma_v3_0_start(struct amdgpu_device *adev)
0792 {
0793     int r;
0794 
0795     /* disable sdma engine before programing it */
0796     sdma_v3_0_ctx_switch_enable(adev, false);
0797     sdma_v3_0_enable(adev, false);
0798 
0799     /* start the gfx rings and rlc compute queues */
0800     r = sdma_v3_0_gfx_resume(adev);
0801     if (r)
0802         return r;
0803     r = sdma_v3_0_rlc_resume(adev);
0804     if (r)
0805         return r;
0806 
0807     return 0;
0808 }
0809 
0810 /**
0811  * sdma_v3_0_ring_test_ring - simple async dma engine test
0812  *
0813  * @ring: amdgpu_ring structure holding ring information
0814  *
0815  * Test the DMA engine by writing using it to write an
0816  * value to memory. (VI).
0817  * Returns 0 for success, error for failure.
0818  */
0819 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
0820 {
0821     struct amdgpu_device *adev = ring->adev;
0822     unsigned i;
0823     unsigned index;
0824     int r;
0825     u32 tmp;
0826     u64 gpu_addr;
0827 
0828     r = amdgpu_device_wb_get(adev, &index);
0829     if (r)
0830         return r;
0831 
0832     gpu_addr = adev->wb.gpu_addr + (index * 4);
0833     tmp = 0xCAFEDEAD;
0834     adev->wb.wb[index] = cpu_to_le32(tmp);
0835 
0836     r = amdgpu_ring_alloc(ring, 5);
0837     if (r)
0838         goto error_free_wb;
0839 
0840     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
0841               SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
0842     amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
0843     amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
0844     amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
0845     amdgpu_ring_write(ring, 0xDEADBEEF);
0846     amdgpu_ring_commit(ring);
0847 
0848     for (i = 0; i < adev->usec_timeout; i++) {
0849         tmp = le32_to_cpu(adev->wb.wb[index]);
0850         if (tmp == 0xDEADBEEF)
0851             break;
0852         udelay(1);
0853     }
0854 
0855     if (i >= adev->usec_timeout)
0856         r = -ETIMEDOUT;
0857 
0858 error_free_wb:
0859     amdgpu_device_wb_free(adev, index);
0860     return r;
0861 }
0862 
0863 /**
0864  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
0865  *
0866  * @ring: amdgpu_ring structure holding ring information
0867  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
0868  *
0869  * Test a simple IB in the DMA ring (VI).
0870  * Returns 0 on success, error on failure.
0871  */
0872 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
0873 {
0874     struct amdgpu_device *adev = ring->adev;
0875     struct amdgpu_ib ib;
0876     struct dma_fence *f = NULL;
0877     unsigned index;
0878     u32 tmp = 0;
0879     u64 gpu_addr;
0880     long r;
0881 
0882     r = amdgpu_device_wb_get(adev, &index);
0883     if (r)
0884         return r;
0885 
0886     gpu_addr = adev->wb.gpu_addr + (index * 4);
0887     tmp = 0xCAFEDEAD;
0888     adev->wb.wb[index] = cpu_to_le32(tmp);
0889     memset(&ib, 0, sizeof(ib));
0890     r = amdgpu_ib_get(adev, NULL, 256,
0891                     AMDGPU_IB_POOL_DIRECT, &ib);
0892     if (r)
0893         goto err0;
0894 
0895     ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
0896         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
0897     ib.ptr[1] = lower_32_bits(gpu_addr);
0898     ib.ptr[2] = upper_32_bits(gpu_addr);
0899     ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
0900     ib.ptr[4] = 0xDEADBEEF;
0901     ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
0902     ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
0903     ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
0904     ib.length_dw = 8;
0905 
0906     r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
0907     if (r)
0908         goto err1;
0909 
0910     r = dma_fence_wait_timeout(f, false, timeout);
0911     if (r == 0) {
0912         r = -ETIMEDOUT;
0913         goto err1;
0914     } else if (r < 0) {
0915         goto err1;
0916     }
0917     tmp = le32_to_cpu(adev->wb.wb[index]);
0918     if (tmp == 0xDEADBEEF)
0919         r = 0;
0920     else
0921         r = -EINVAL;
0922 err1:
0923     amdgpu_ib_free(adev, &ib, NULL);
0924     dma_fence_put(f);
0925 err0:
0926     amdgpu_device_wb_free(adev, index);
0927     return r;
0928 }
0929 
0930 /**
0931  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
0932  *
0933  * @ib: indirect buffer to fill with commands
0934  * @pe: addr of the page entry
0935  * @src: src addr to copy from
0936  * @count: number of page entries to update
0937  *
0938  * Update PTEs by copying them from the GART using sDMA (CIK).
0939  */
0940 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
0941                   uint64_t pe, uint64_t src,
0942                   unsigned count)
0943 {
0944     unsigned bytes = count * 8;
0945 
0946     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
0947         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
0948     ib->ptr[ib->length_dw++] = bytes;
0949     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
0950     ib->ptr[ib->length_dw++] = lower_32_bits(src);
0951     ib->ptr[ib->length_dw++] = upper_32_bits(src);
0952     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
0953     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
0954 }
0955 
0956 /**
0957  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
0958  *
0959  * @ib: indirect buffer to fill with commands
0960  * @pe: addr of the page entry
0961  * @value: dst addr to write into pe
0962  * @count: number of page entries to update
0963  * @incr: increase next addr by incr bytes
0964  *
0965  * Update PTEs by writing them manually using sDMA (CIK).
0966  */
0967 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
0968                    uint64_t value, unsigned count,
0969                    uint32_t incr)
0970 {
0971     unsigned ndw = count * 2;
0972 
0973     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
0974         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
0975     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
0976     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
0977     ib->ptr[ib->length_dw++] = ndw;
0978     for (; ndw > 0; ndw -= 2) {
0979         ib->ptr[ib->length_dw++] = lower_32_bits(value);
0980         ib->ptr[ib->length_dw++] = upper_32_bits(value);
0981         value += incr;
0982     }
0983 }
0984 
0985 /**
0986  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
0987  *
0988  * @ib: indirect buffer to fill with commands
0989  * @pe: addr of the page entry
0990  * @addr: dst addr to write into pe
0991  * @count: number of page entries to update
0992  * @incr: increase next addr by incr bytes
0993  * @flags: access flags
0994  *
0995  * Update the page tables using sDMA (CIK).
0996  */
0997 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
0998                      uint64_t addr, unsigned count,
0999                      uint32_t incr, uint64_t flags)
1000 {
1001     /* for physically contiguous pages (vram) */
1002     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1003     ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1004     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1005     ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1006     ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1007     ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1008     ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1009     ib->ptr[ib->length_dw++] = incr; /* increment size */
1010     ib->ptr[ib->length_dw++] = 0;
1011     ib->ptr[ib->length_dw++] = count; /* number of entries */
1012 }
1013 
1014 /**
1015  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1016  *
1017  * @ring: amdgpu_ring structure holding ring information
1018  * @ib: indirect buffer to fill with padding
1019  *
1020  */
1021 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1022 {
1023     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1024     u32 pad_count;
1025     int i;
1026 
1027     pad_count = (-ib->length_dw) & 7;
1028     for (i = 0; i < pad_count; i++)
1029         if (sdma && sdma->burst_nop && (i == 0))
1030             ib->ptr[ib->length_dw++] =
1031                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1032                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1033         else
1034             ib->ptr[ib->length_dw++] =
1035                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1036 }
1037 
1038 /**
1039  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1040  *
1041  * @ring: amdgpu_ring pointer
1042  *
1043  * Make sure all previous operations are completed (CIK).
1044  */
1045 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1046 {
1047     uint32_t seq = ring->fence_drv.sync_seq;
1048     uint64_t addr = ring->fence_drv.gpu_addr;
1049 
1050     /* wait for idle */
1051     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1052               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1053               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1054               SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1055     amdgpu_ring_write(ring, addr & 0xfffffffc);
1056     amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1057     amdgpu_ring_write(ring, seq); /* reference */
1058     amdgpu_ring_write(ring, 0xffffffff); /* mask */
1059     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1060               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1061 }
1062 
1063 /**
1064  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1065  *
1066  * @ring: amdgpu_ring pointer
1067  * @vmid: vmid number to use
1068  * @pd_addr: address
1069  *
1070  * Update the page table base and flush the VM TLB
1071  * using sDMA (VI).
1072  */
1073 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1074                      unsigned vmid, uint64_t pd_addr)
1075 {
1076     amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1077 
1078     /* wait for flush */
1079     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1080               SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1081               SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1082     amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1083     amdgpu_ring_write(ring, 0);
1084     amdgpu_ring_write(ring, 0); /* reference */
1085     amdgpu_ring_write(ring, 0); /* mask */
1086     amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1087               SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1088 }
1089 
1090 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1091                      uint32_t reg, uint32_t val)
1092 {
1093     amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1094               SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1095     amdgpu_ring_write(ring, reg);
1096     amdgpu_ring_write(ring, val);
1097 }
1098 
1099 static int sdma_v3_0_early_init(void *handle)
1100 {
1101     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102 
1103     switch (adev->asic_type) {
1104     case CHIP_STONEY:
1105         adev->sdma.num_instances = 1;
1106         break;
1107     default:
1108         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1109         break;
1110     }
1111 
1112     sdma_v3_0_set_ring_funcs(adev);
1113     sdma_v3_0_set_buffer_funcs(adev);
1114     sdma_v3_0_set_vm_pte_funcs(adev);
1115     sdma_v3_0_set_irq_funcs(adev);
1116 
1117     return 0;
1118 }
1119 
1120 static int sdma_v3_0_sw_init(void *handle)
1121 {
1122     struct amdgpu_ring *ring;
1123     int r, i;
1124     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1125 
1126     /* SDMA trap event */
1127     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1128                   &adev->sdma.trap_irq);
1129     if (r)
1130         return r;
1131 
1132     /* SDMA Privileged inst */
1133     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1134                   &adev->sdma.illegal_inst_irq);
1135     if (r)
1136         return r;
1137 
1138     /* SDMA Privileged inst */
1139     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1140                   &adev->sdma.illegal_inst_irq);
1141     if (r)
1142         return r;
1143 
1144     r = sdma_v3_0_init_microcode(adev);
1145     if (r) {
1146         DRM_ERROR("Failed to load sdma firmware!\n");
1147         return r;
1148     }
1149 
1150     for (i = 0; i < adev->sdma.num_instances; i++) {
1151         ring = &adev->sdma.instance[i].ring;
1152         ring->ring_obj = NULL;
1153         if (!amdgpu_sriov_vf(adev)) {
1154             ring->use_doorbell = true;
1155             ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1156         } else {
1157             ring->use_pollmem = true;
1158         }
1159 
1160         sprintf(ring->name, "sdma%d", i);
1161         r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1162                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1163                      AMDGPU_SDMA_IRQ_INSTANCE1,
1164                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1165         if (r)
1166             return r;
1167     }
1168 
1169     return r;
1170 }
1171 
1172 static int sdma_v3_0_sw_fini(void *handle)
1173 {
1174     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175     int i;
1176 
1177     for (i = 0; i < adev->sdma.num_instances; i++)
1178         amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1179 
1180     sdma_v3_0_free_microcode(adev);
1181     return 0;
1182 }
1183 
1184 static int sdma_v3_0_hw_init(void *handle)
1185 {
1186     int r;
1187     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1188 
1189     sdma_v3_0_init_golden_registers(adev);
1190 
1191     r = sdma_v3_0_start(adev);
1192     if (r)
1193         return r;
1194 
1195     return r;
1196 }
1197 
1198 static int sdma_v3_0_hw_fini(void *handle)
1199 {
1200     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1201 
1202     sdma_v3_0_ctx_switch_enable(adev, false);
1203     sdma_v3_0_enable(adev, false);
1204 
1205     return 0;
1206 }
1207 
1208 static int sdma_v3_0_suspend(void *handle)
1209 {
1210     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1211 
1212     return sdma_v3_0_hw_fini(adev);
1213 }
1214 
1215 static int sdma_v3_0_resume(void *handle)
1216 {
1217     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218 
1219     return sdma_v3_0_hw_init(adev);
1220 }
1221 
1222 static bool sdma_v3_0_is_idle(void *handle)
1223 {
1224     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225     u32 tmp = RREG32(mmSRBM_STATUS2);
1226 
1227     if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1228            SRBM_STATUS2__SDMA1_BUSY_MASK))
1229         return false;
1230 
1231     return true;
1232 }
1233 
1234 static int sdma_v3_0_wait_for_idle(void *handle)
1235 {
1236     unsigned i;
1237     u32 tmp;
1238     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1239 
1240     for (i = 0; i < adev->usec_timeout; i++) {
1241         tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1242                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1243 
1244         if (!tmp)
1245             return 0;
1246         udelay(1);
1247     }
1248     return -ETIMEDOUT;
1249 }
1250 
1251 static bool sdma_v3_0_check_soft_reset(void *handle)
1252 {
1253     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1254     u32 srbm_soft_reset = 0;
1255     u32 tmp = RREG32(mmSRBM_STATUS2);
1256 
1257     if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1258         (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1259         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1260         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1261     }
1262 
1263     if (srbm_soft_reset) {
1264         adev->sdma.srbm_soft_reset = srbm_soft_reset;
1265         return true;
1266     } else {
1267         adev->sdma.srbm_soft_reset = 0;
1268         return false;
1269     }
1270 }
1271 
1272 static int sdma_v3_0_pre_soft_reset(void *handle)
1273 {
1274     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1275     u32 srbm_soft_reset = 0;
1276 
1277     if (!adev->sdma.srbm_soft_reset)
1278         return 0;
1279 
1280     srbm_soft_reset = adev->sdma.srbm_soft_reset;
1281 
1282     if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1283         REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1284         sdma_v3_0_ctx_switch_enable(adev, false);
1285         sdma_v3_0_enable(adev, false);
1286     }
1287 
1288     return 0;
1289 }
1290 
1291 static int sdma_v3_0_post_soft_reset(void *handle)
1292 {
1293     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1294     u32 srbm_soft_reset = 0;
1295 
1296     if (!adev->sdma.srbm_soft_reset)
1297         return 0;
1298 
1299     srbm_soft_reset = adev->sdma.srbm_soft_reset;
1300 
1301     if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1302         REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1303         sdma_v3_0_gfx_resume(adev);
1304         sdma_v3_0_rlc_resume(adev);
1305     }
1306 
1307     return 0;
1308 }
1309 
1310 static int sdma_v3_0_soft_reset(void *handle)
1311 {
1312     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313     u32 srbm_soft_reset = 0;
1314     u32 tmp;
1315 
1316     if (!adev->sdma.srbm_soft_reset)
1317         return 0;
1318 
1319     srbm_soft_reset = adev->sdma.srbm_soft_reset;
1320 
1321     if (srbm_soft_reset) {
1322         tmp = RREG32(mmSRBM_SOFT_RESET);
1323         tmp |= srbm_soft_reset;
1324         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1325         WREG32(mmSRBM_SOFT_RESET, tmp);
1326         tmp = RREG32(mmSRBM_SOFT_RESET);
1327 
1328         udelay(50);
1329 
1330         tmp &= ~srbm_soft_reset;
1331         WREG32(mmSRBM_SOFT_RESET, tmp);
1332         tmp = RREG32(mmSRBM_SOFT_RESET);
1333 
1334         /* Wait a little for things to settle down */
1335         udelay(50);
1336     }
1337 
1338     return 0;
1339 }
1340 
1341 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1342                     struct amdgpu_irq_src *source,
1343                     unsigned type,
1344                     enum amdgpu_interrupt_state state)
1345 {
1346     u32 sdma_cntl;
1347 
1348     switch (type) {
1349     case AMDGPU_SDMA_IRQ_INSTANCE0:
1350         switch (state) {
1351         case AMDGPU_IRQ_STATE_DISABLE:
1352             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1353             sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1354             WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1355             break;
1356         case AMDGPU_IRQ_STATE_ENABLE:
1357             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1358             sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1359             WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1360             break;
1361         default:
1362             break;
1363         }
1364         break;
1365     case AMDGPU_SDMA_IRQ_INSTANCE1:
1366         switch (state) {
1367         case AMDGPU_IRQ_STATE_DISABLE:
1368             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1369             sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1370             WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1371             break;
1372         case AMDGPU_IRQ_STATE_ENABLE:
1373             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1374             sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1375             WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1376             break;
1377         default:
1378             break;
1379         }
1380         break;
1381     default:
1382         break;
1383     }
1384     return 0;
1385 }
1386 
1387 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1388                       struct amdgpu_irq_src *source,
1389                       struct amdgpu_iv_entry *entry)
1390 {
1391     u8 instance_id, queue_id;
1392 
1393     instance_id = (entry->ring_id & 0x3) >> 0;
1394     queue_id = (entry->ring_id & 0xc) >> 2;
1395     DRM_DEBUG("IH: SDMA trap\n");
1396     switch (instance_id) {
1397     case 0:
1398         switch (queue_id) {
1399         case 0:
1400             amdgpu_fence_process(&adev->sdma.instance[0].ring);
1401             break;
1402         case 1:
1403             /* XXX compute */
1404             break;
1405         case 2:
1406             /* XXX compute */
1407             break;
1408         }
1409         break;
1410     case 1:
1411         switch (queue_id) {
1412         case 0:
1413             amdgpu_fence_process(&adev->sdma.instance[1].ring);
1414             break;
1415         case 1:
1416             /* XXX compute */
1417             break;
1418         case 2:
1419             /* XXX compute */
1420             break;
1421         }
1422         break;
1423     }
1424     return 0;
1425 }
1426 
1427 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1428                           struct amdgpu_irq_src *source,
1429                           struct amdgpu_iv_entry *entry)
1430 {
1431     u8 instance_id, queue_id;
1432 
1433     DRM_ERROR("Illegal instruction in SDMA command stream\n");
1434     instance_id = (entry->ring_id & 0x3) >> 0;
1435     queue_id = (entry->ring_id & 0xc) >> 2;
1436 
1437     if (instance_id <= 1 && queue_id == 0)
1438         drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1439     return 0;
1440 }
1441 
1442 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1443         struct amdgpu_device *adev,
1444         bool enable)
1445 {
1446     uint32_t temp, data;
1447     int i;
1448 
1449     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1450         for (i = 0; i < adev->sdma.num_instances; i++) {
1451             temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1452             data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1453                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1454                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1455                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1456                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1457                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1458                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1459                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1460             if (data != temp)
1461                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1462         }
1463     } else {
1464         for (i = 0; i < adev->sdma.num_instances; i++) {
1465             temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1466             data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1467                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1468                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1469                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1470                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1471                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1472                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1473                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1474 
1475             if (data != temp)
1476                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1477         }
1478     }
1479 }
1480 
1481 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1482         struct amdgpu_device *adev,
1483         bool enable)
1484 {
1485     uint32_t temp, data;
1486     int i;
1487 
1488     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1489         for (i = 0; i < adev->sdma.num_instances; i++) {
1490             temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1491             data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1492 
1493             if (temp != data)
1494                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1495         }
1496     } else {
1497         for (i = 0; i < adev->sdma.num_instances; i++) {
1498             temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1499             data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1500 
1501             if (temp != data)
1502                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1503         }
1504     }
1505 }
1506 
1507 static int sdma_v3_0_set_clockgating_state(void *handle,
1508                       enum amd_clockgating_state state)
1509 {
1510     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1511 
1512     if (amdgpu_sriov_vf(adev))
1513         return 0;
1514 
1515     switch (adev->asic_type) {
1516     case CHIP_FIJI:
1517     case CHIP_CARRIZO:
1518     case CHIP_STONEY:
1519         sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1520                 state == AMD_CG_STATE_GATE);
1521         sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1522                 state == AMD_CG_STATE_GATE);
1523         break;
1524     default:
1525         break;
1526     }
1527     return 0;
1528 }
1529 
1530 static int sdma_v3_0_set_powergating_state(void *handle,
1531                       enum amd_powergating_state state)
1532 {
1533     return 0;
1534 }
1535 
1536 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags)
1537 {
1538     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1539     int data;
1540 
1541     if (amdgpu_sriov_vf(adev))
1542         *flags = 0;
1543 
1544     /* AMD_CG_SUPPORT_SDMA_MGCG */
1545     data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1546     if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1547         *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1548 
1549     /* AMD_CG_SUPPORT_SDMA_LS */
1550     data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1551     if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1552         *flags |= AMD_CG_SUPPORT_SDMA_LS;
1553 }
1554 
1555 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1556     .name = "sdma_v3_0",
1557     .early_init = sdma_v3_0_early_init,
1558     .late_init = NULL,
1559     .sw_init = sdma_v3_0_sw_init,
1560     .sw_fini = sdma_v3_0_sw_fini,
1561     .hw_init = sdma_v3_0_hw_init,
1562     .hw_fini = sdma_v3_0_hw_fini,
1563     .suspend = sdma_v3_0_suspend,
1564     .resume = sdma_v3_0_resume,
1565     .is_idle = sdma_v3_0_is_idle,
1566     .wait_for_idle = sdma_v3_0_wait_for_idle,
1567     .check_soft_reset = sdma_v3_0_check_soft_reset,
1568     .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1569     .post_soft_reset = sdma_v3_0_post_soft_reset,
1570     .soft_reset = sdma_v3_0_soft_reset,
1571     .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1572     .set_powergating_state = sdma_v3_0_set_powergating_state,
1573     .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1574 };
1575 
1576 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1577     .type = AMDGPU_RING_TYPE_SDMA,
1578     .align_mask = 0xf,
1579     .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1580     .support_64bit_ptrs = false,
1581     .secure_submission_supported = true,
1582     .get_rptr = sdma_v3_0_ring_get_rptr,
1583     .get_wptr = sdma_v3_0_ring_get_wptr,
1584     .set_wptr = sdma_v3_0_ring_set_wptr,
1585     .emit_frame_size =
1586         6 + /* sdma_v3_0_ring_emit_hdp_flush */
1587         3 + /* hdp invalidate */
1588         6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1589         VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1590         10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1591     .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1592     .emit_ib = sdma_v3_0_ring_emit_ib,
1593     .emit_fence = sdma_v3_0_ring_emit_fence,
1594     .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1595     .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1596     .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1597     .test_ring = sdma_v3_0_ring_test_ring,
1598     .test_ib = sdma_v3_0_ring_test_ib,
1599     .insert_nop = sdma_v3_0_ring_insert_nop,
1600     .pad_ib = sdma_v3_0_ring_pad_ib,
1601     .emit_wreg = sdma_v3_0_ring_emit_wreg,
1602 };
1603 
1604 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1605 {
1606     int i;
1607 
1608     for (i = 0; i < adev->sdma.num_instances; i++) {
1609         adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1610         adev->sdma.instance[i].ring.me = i;
1611     }
1612 }
1613 
1614 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1615     .set = sdma_v3_0_set_trap_irq_state,
1616     .process = sdma_v3_0_process_trap_irq,
1617 };
1618 
1619 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1620     .process = sdma_v3_0_process_illegal_inst_irq,
1621 };
1622 
1623 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1624 {
1625     adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1626     adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1627     adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1628 }
1629 
1630 /**
1631  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1632  *
1633  * @ib: indirect buffer to copy to
1634  * @src_offset: src GPU address
1635  * @dst_offset: dst GPU address
1636  * @byte_count: number of bytes to xfer
1637  * @tmz: unused
1638  *
1639  * Copy GPU buffers using the DMA engine (VI).
1640  * Used by the amdgpu ttm implementation to move pages if
1641  * registered as the asic copy callback.
1642  */
1643 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1644                        uint64_t src_offset,
1645                        uint64_t dst_offset,
1646                        uint32_t byte_count,
1647                        bool tmz)
1648 {
1649     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1650         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1651     ib->ptr[ib->length_dw++] = byte_count;
1652     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1653     ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1654     ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1655     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1656     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1657 }
1658 
1659 /**
1660  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1661  *
1662  * @ib: indirect buffer to copy to
1663  * @src_data: value to write to buffer
1664  * @dst_offset: dst GPU address
1665  * @byte_count: number of bytes to xfer
1666  *
1667  * Fill GPU buffers using the DMA engine (VI).
1668  */
1669 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1670                        uint32_t src_data,
1671                        uint64_t dst_offset,
1672                        uint32_t byte_count)
1673 {
1674     ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1675     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1676     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1677     ib->ptr[ib->length_dw++] = src_data;
1678     ib->ptr[ib->length_dw++] = byte_count;
1679 }
1680 
1681 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1682     .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1683     .copy_num_dw = 7,
1684     .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1685 
1686     .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1687     .fill_num_dw = 5,
1688     .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1689 };
1690 
1691 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1692 {
1693     adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1694     adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1695 }
1696 
1697 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1698     .copy_pte_num_dw = 7,
1699     .copy_pte = sdma_v3_0_vm_copy_pte,
1700 
1701     .write_pte = sdma_v3_0_vm_write_pte,
1702     .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1703 };
1704 
1705 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1706 {
1707     unsigned i;
1708 
1709     adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1710     for (i = 0; i < adev->sdma.num_instances; i++) {
1711         adev->vm_manager.vm_pte_scheds[i] =
1712              &adev->sdma.instance[i].ring.sched;
1713     }
1714     adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1715 }
1716 
1717 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1718 {
1719     .type = AMD_IP_BLOCK_TYPE_SDMA,
1720     .major = 3,
1721     .minor = 0,
1722     .rev = 0,
1723     .funcs = &sdma_v3_0_ip_funcs,
1724 };
1725 
1726 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1727 {
1728     .type = AMD_IP_BLOCK_TYPE_SDMA,
1729     .major = 3,
1730     .minor = 1,
1731     .rev = 0,
1732     .funcs = &sdma_v3_0_ip_funcs,
1733 };
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