amd/amdgpu/psp_v3_1.c

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Author: Huang Rui
0023  *
0024  */
0025
0026 #include <linux/firmware.h>
0027 #include <linux/module.h>
0028 #include <linux/pci.h>
0029
0030 #include "amdgpu.h"
0031 #include "amdgpu_psp.h"
0032 #include "amdgpu_ucode.h"
0033 #include "soc15_common.h"
0034 #include "psp_v3_1.h"
0035
0036 #include "mp/mp_9_0_offset.h"
0037 #include "mp/mp_9_0_sh_mask.h"
0038 #include "gc/gc_9_0_offset.h"
0039 #include "sdma0/sdma0_4_0_offset.h"
0040 #include "nbio/nbio_6_1_offset.h"
0041
0042 #include "oss/osssys_4_0_offset.h"
0043 #include "oss/osssys_4_0_sh_mask.h"
0044
0045 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
0046 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
0047 MODULE_FIRMWARE("amdgpu/vega10_cap.bin");
0048 MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
0049 MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
0050
0051
0052 #define smnMP1_FIRMWARE_FLAGS 0x3010028
0053
0054 static int psp_v3_1_ring_stop(struct psp_context *psp,
0055                   enum psp_ring_type ring_type);
0056
0057 static int psp_v3_1_init_microcode(struct psp_context *psp)
0058 {
0059     struct amdgpu_device *adev = psp->adev;
0060     const char *chip_name;
0061     int err = 0;
0062
0063     DRM_DEBUG("\n");
0064
0065     switch (adev->asic_type) {
0066     case CHIP_VEGA10:
0067         chip_name = "vega10";
0068         break;
0069     case CHIP_VEGA12:
0070         chip_name = "vega12";
0071         break;
0072     default: BUG();
0073     }
0074
0075     err = psp_init_sos_microcode(psp, chip_name);
0076     if (err)
0077         return err;
0078
0079     err = psp_init_asd_microcode(psp, chip_name);
0080     if (err)
0081         return err;
0082
0083     return 0;
0084 }
0085
0086 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
0087 {
0088     int ret;
0089     uint32_t psp_gfxdrv_command_reg = 0;
0090     struct amdgpu_device *adev = psp->adev;
0091     uint32_t sol_reg;
0092
0093     /* Check sOS sign of life register to confirm sys driver and sOS
0094      * are already been loaded.
0095      */
0096     sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
0097     if (sol_reg)
0098         return 0;
0099
0100     /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
0101     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0102                0x80000000, 0x80000000, false);
0103     if (ret)
0104         return ret;
0105
0106     /* Copy PSP System Driver binary to memory */
0107     psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
0108
0109     /* Provide the sys driver to bootloader */
0110     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
0111            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0112     psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
0113     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
0114            psp_gfxdrv_command_reg);
0115
0116     /* there might be handshake issue with hardware which needs delay */
0117     mdelay(20);
0118
0119     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0120                0x80000000, 0x80000000, false);
0121
0122     return ret;
0123 }
0124
0125 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
0126 {
0127     int ret;
0128     unsigned int psp_gfxdrv_command_reg = 0;
0129     struct amdgpu_device *adev = psp->adev;
0130     uint32_t sol_reg;
0131
0132     /* Check sOS sign of life register to confirm sys driver and sOS
0133      * are already been loaded.
0134      */
0135     sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
0136     if (sol_reg)
0137         return 0;
0138
0139     /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
0140     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0141                0x80000000, 0x80000000, false);
0142     if (ret)
0143         return ret;
0144
0145     /* Copy Secure OS binary to PSP memory */
0146     psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
0147
0148     /* Provide the PSP secure OS to bootloader */
0149     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
0150            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0151     psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
0152     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
0153            psp_gfxdrv_command_reg);
0154
0155     /* there might be handshake issue with hardware which needs delay */
0156     mdelay(20);
0157     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
0158                RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
0159                0, true);
0160     return ret;
0161 }
0162
0163 static int psp_v3_1_ring_init(struct psp_context *psp,
0164                   enum psp_ring_type ring_type)
0165 {
0166     int ret = 0;
0167     struct psp_ring *ring;
0168     struct amdgpu_device *adev = psp->adev;
0169
0170     ring = &psp->km_ring;
0171
0172     ring->ring_type = ring_type;
0173
0174     /* allocate 4k Page of Local Frame Buffer memory for ring */
0175     ring->ring_size = 0x1000;
0176     ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
0177                       AMDGPU_GEM_DOMAIN_VRAM,
0178                       &adev->firmware.rbuf,
0179                       &ring->ring_mem_mc_addr,
0180                       (void **)&ring->ring_mem);
0181     if (ret) {
0182         ring->ring_size = 0;
0183         return ret;
0184     }
0185
0186     return 0;
0187 }
0188
0189 static void psp_v3_1_reroute_ih(struct psp_context *psp)
0190 {
0191     struct amdgpu_device *adev = psp->adev;
0192     uint32_t tmp;
0193
0194     /* Change IH ring for VMC */
0195     tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
0196     tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
0197     tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
0198
0199     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
0200     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
0201     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
0202
0203     mdelay(20);
0204     psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0205              0x80000000, 0x8000FFFF, false);
0206
0207     /* Change IH ring for UMC */
0208     tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
0209     tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
0210
0211     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
0212     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
0213     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
0214
0215     mdelay(20);
0216     psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0217              0x80000000, 0x8000FFFF, false);
0218 }
0219
0220 static int psp_v3_1_ring_create(struct psp_context *psp,
0221                 enum psp_ring_type ring_type)
0222 {
0223     int ret = 0;
0224     unsigned int psp_ring_reg = 0;
0225     struct psp_ring *ring = &psp->km_ring;
0226     struct amdgpu_device *adev = psp->adev;
0227
0228     psp_v3_1_reroute_ih(psp);
0229
0230     if (amdgpu_sriov_vf(adev)) {
0231         ring->ring_wptr = 0;
0232         ret = psp_v3_1_ring_stop(psp, ring_type);
0233         if (ret) {
0234             DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
0235             return ret;
0236         }
0237
0238         /* Write low address of the ring to C2PMSG_102 */
0239         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0240         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
0241         /* Write high address of the ring to C2PMSG_103 */
0242         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0243         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
0244         /* No size initialization for sriov  */
0245         /* Write the ring initialization command to C2PMSG_101 */
0246         psp_ring_reg = ring_type;
0247         psp_ring_reg = psp_ring_reg << 16;
0248         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
0249
0250         /* there might be hardware handshake issue which needs delay */
0251         mdelay(20);
0252
0253         /* Wait for response flag (bit 31) in C2PMSG_101 */
0254         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
0255                     mmMP0_SMN_C2PMSG_101), 0x80000000,
0256                     0x8000FFFF, false);
0257     } else {
0258
0259         /* Write low address of the ring to C2PMSG_69 */
0260         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0261         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
0262         /* Write high address of the ring to C2PMSG_70 */
0263         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0264         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
0265         /* Write size of ring to C2PMSG_71 */
0266         psp_ring_reg = ring->ring_size;
0267         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
0268         /* Write the ring initialization command to C2PMSG_64 */
0269         psp_ring_reg = ring_type;
0270         psp_ring_reg = psp_ring_reg << 16;
0271         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
0272
0273         /* there might be hardware handshake issue which needs delay */
0274         mdelay(20);
0275
0276         /* Wait for response flag (bit 31) in C2PMSG_64 */
0277         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
0278                     mmMP0_SMN_C2PMSG_64), 0x80000000,
0279                     0x8000FFFF, false);
0280
0281     }
0282     return ret;
0283 }
0284
0285 static int psp_v3_1_ring_stop(struct psp_context *psp,
0286                   enum psp_ring_type ring_type)
0287 {
0288     int ret = 0;
0289     struct amdgpu_device *adev = psp->adev;
0290
0291     /* Write the ring destroy command*/
0292     if (amdgpu_sriov_vf(adev))
0293         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0294                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
0295     else
0296         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
0297                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
0298
0299     /* there might be handshake issue with hardware which needs delay */
0300     mdelay(20);
0301
0302     /* Wait for response flag (bit 31) */
0303     if (amdgpu_sriov_vf(adev))
0304         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0305                    0x80000000, 0x80000000, false);
0306     else
0307         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0308                    0x80000000, 0x80000000, false);
0309
0310     return ret;
0311 }
0312
0313 static int psp_v3_1_ring_destroy(struct psp_context *psp,
0314                  enum psp_ring_type ring_type)
0315 {
0316     int ret = 0;
0317     struct psp_ring *ring = &psp->km_ring;
0318     struct amdgpu_device *adev = psp->adev;
0319
0320     ret = psp_v3_1_ring_stop(psp, ring_type);
0321     if (ret)
0322         DRM_ERROR("Fail to stop psp ring\n");
0323
0324     amdgpu_bo_free_kernel(&adev->firmware.rbuf,
0325                   &ring->ring_mem_mc_addr,
0326                   (void **)&ring->ring_mem);
0327
0328     return ret;
0329 }
0330
0331 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
0332 {
0333     struct amdgpu_device *adev = psp->adev;
0334     uint32_t reg;
0335
0336     reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
0337     return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
0338 }
0339
0340 static int psp_v3_1_mode1_reset(struct psp_context *psp)
0341 {
0342     int ret;
0343     uint32_t offset;
0344     struct amdgpu_device *adev = psp->adev;
0345
0346     offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
0347
0348     ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
0349
0350     if (ret) {
0351         DRM_INFO("psp is not working correctly before mode1 reset!\n");
0352         return -EINVAL;
0353     }
0354
0355     /*send the mode 1 reset command*/
0356     WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
0357
0358     msleep(500);
0359
0360     offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
0361
0362     ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
0363
0364     if (ret) {
0365         DRM_INFO("psp mode 1 reset failed!\n");
0366         return -EINVAL;
0367     }
0368
0369     DRM_INFO("psp mode1 reset succeed \n");
0370
0371     return 0;
0372 }
0373
0374 static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
0375 {
0376     uint32_t data;
0377     struct amdgpu_device *adev = psp->adev;
0378
0379     if (amdgpu_sriov_vf(adev))
0380         data = psp->km_ring.ring_wptr;
0381     else
0382         data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
0383     return data;
0384 }
0385
0386 static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
0387 {
0388     struct amdgpu_device *adev = psp->adev;
0389
0390     if (amdgpu_sriov_vf(adev)) {
0391         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
0392         /* send interrupt to PSP for SRIOV ring write pointer update */
0393         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0394             GFX_CTRL_CMD_ID_CONSUME_CMD);
0395         psp->km_ring.ring_wptr = value;
0396     } else
0397         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
0398 }
0399
0400 static const struct psp_funcs psp_v3_1_funcs = {
0401     .init_microcode = psp_v3_1_init_microcode,
0402     .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
0403     .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
0404     .ring_init = psp_v3_1_ring_init,
0405     .ring_create = psp_v3_1_ring_create,
0406     .ring_stop = psp_v3_1_ring_stop,
0407     .ring_destroy = psp_v3_1_ring_destroy,
0408     .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
0409     .mode1_reset = psp_v3_1_mode1_reset,
0410     .ring_get_wptr = psp_v3_1_ring_get_wptr,
0411     .ring_set_wptr = psp_v3_1_ring_set_wptr,
0412 };
0413
0414 void psp_v3_1_set_psp_funcs(struct psp_context *psp)
0415 {
0416     psp->funcs = &psp_v3_1_funcs;
0417 }