amd/amdgpu/psp_v13_0_4.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "amdgpu_psp.h"
0025 #include "amdgpu_ucode.h"
0026 #include "soc15_common.h"
0027 #include "psp_v13_0_4.h"
0028
0029 #include "mp/mp_13_0_4_offset.h"
0030 #include "mp/mp_13_0_4_sh_mask.h"
0031
0032 MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
0033 MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
0034
0035 static int psp_v13_0_4_init_microcode(struct psp_context *psp)
0036 {
0037     struct amdgpu_device *adev = psp->adev;
0038     const char *chip_name;
0039     char ucode_prefix[30];
0040     int err = 0;
0041
0042     switch (adev->ip_versions[MP0_HWIP][0]) {
0043     case IP_VERSION(13, 0, 4):
0044         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
0045         chip_name = ucode_prefix;
0046         break;
0047     default:
0048         BUG();
0049     }
0050
0051     switch (adev->ip_versions[MP0_HWIP][0]) {
0052     case IP_VERSION(13, 0, 4):
0053         err = psp_init_toc_microcode(psp, chip_name);
0054         if (err)
0055             return err;
0056         err = psp_init_ta_microcode(psp, chip_name);
0057         if (err)
0058             return err;
0059         break;
0060     default:
0061         BUG();
0062     }
0063
0064     return 0;
0065 }
0066
0067 static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
0068 {
0069     struct amdgpu_device *adev = psp->adev;
0070     uint32_t sol_reg;
0071
0072     sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
0073
0074     return sol_reg != 0x0;
0075 }
0076
0077 static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
0078 {
0079     struct amdgpu_device *adev = psp->adev;
0080
0081     int ret;
0082     int retry_loop;
0083
0084     for (retry_loop = 0; retry_loop < 10; retry_loop++) {
0085         /* Wait for bootloader to signify that is
0086             ready having bit 31 of C2PMSG_35 set to 1 */
0087         ret = psp_wait_for(psp,
0088                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0089                    0x80000000,
0090                    0x80000000,
0091                    false);
0092
0093         if (ret == 0)
0094             return 0;
0095     }
0096
0097     return ret;
0098 }
0099
0100 static int psp_v13_0_4_bootloader_load_component(struct psp_context     *psp,
0101                            struct psp_bin_desc  *bin_desc,
0102                            enum psp_bootloader_cmd  bl_cmd)
0103 {
0104     int ret;
0105     uint32_t psp_gfxdrv_command_reg = 0;
0106     struct amdgpu_device *adev = psp->adev;
0107
0108     /* Check tOS sign of life register to confirm sys driver and sOS
0109      * are already been loaded.
0110      */
0111     if (psp_v13_0_4_is_sos_alive(psp))
0112         return 0;
0113
0114     ret = psp_v13_0_4_wait_for_bootloader(psp);
0115     if (ret)
0116         return ret;
0117
0118     memset(psp->fw_pri_buf, 0, PSP_1_MEG);
0119
0120     /* Copy PSP KDB binary to memory */
0121     memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
0122
0123     /* Provide the PSP KDB to bootloader */
0124     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
0125            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0126     psp_gfxdrv_command_reg = bl_cmd;
0127     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
0128            psp_gfxdrv_command_reg);
0129
0130     ret = psp_v13_0_4_wait_for_bootloader(psp);
0131
0132     return ret;
0133 }
0134
0135 static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
0136 {
0137     return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
0138 }
0139
0140 static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
0141 {
0142     return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
0143 }
0144
0145 static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
0146 {
0147     return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
0148 }
0149
0150 static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
0151 {
0152     return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
0153 }
0154
0155 static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
0156 {
0157     return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
0158 }
0159
0160 static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
0161 {
0162     return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
0163 }
0164
0165 static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
0166 {
0167     int ret;
0168     unsigned int psp_gfxdrv_command_reg = 0;
0169     struct amdgpu_device *adev = psp->adev;
0170
0171     /* Check sOS sign of life register to confirm sys driver and sOS
0172      * are already been loaded.
0173      */
0174     if (psp_v13_0_4_is_sos_alive(psp))
0175         return 0;
0176
0177     ret = psp_v13_0_4_wait_for_bootloader(psp);
0178     if (ret)
0179         return ret;
0180
0181     memset(psp->fw_pri_buf, 0, PSP_1_MEG);
0182
0183     /* Copy Secure OS binary to PSP memory */
0184     memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
0185
0186     /* Provide the PSP secure OS to bootloader */
0187     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
0188            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0189     psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
0190     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
0191            psp_gfxdrv_command_reg);
0192
0193     /* there might be handshake issue with hardware which needs delay */
0194     mdelay(20);
0195     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
0196                RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
0197                0, true);
0198
0199     return ret;
0200 }
0201
0202 static int psp_v13_0_4_ring_init(struct psp_context *psp,
0203                   enum psp_ring_type ring_type)
0204 {
0205     int ret = 0;
0206     struct psp_ring *ring;
0207     struct amdgpu_device *adev = psp->adev;
0208
0209     ring = &psp->km_ring;
0210
0211     ring->ring_type = ring_type;
0212
0213     /* allocate 4k Page of Local Frame Buffer memory for ring */
0214     ring->ring_size = 0x1000;
0215     ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
0216                       AMDGPU_GEM_DOMAIN_VRAM,
0217                       &adev->firmware.rbuf,
0218                       &ring->ring_mem_mc_addr,
0219                       (void **)&ring->ring_mem);
0220     if (ret) {
0221         ring->ring_size = 0;
0222         return ret;
0223     }
0224
0225     return 0;
0226 }
0227
0228 static int psp_v13_0_4_ring_stop(struct psp_context *psp,
0229                    enum psp_ring_type ring_type)
0230 {
0231     int ret = 0;
0232     struct amdgpu_device *adev = psp->adev;
0233
0234     if (amdgpu_sriov_vf(adev)) {
0235         /* Write the ring destroy command*/
0236         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
0237                  GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
0238         /* there might be handshake issue with hardware which needs delay */
0239         mdelay(20);
0240         /* Wait for response flag (bit 31) */
0241         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
0242                    0x80000000, 0x80000000, false);
0243     } else {
0244         /* Write the ring destroy command*/
0245         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
0246                  GFX_CTRL_CMD_ID_DESTROY_RINGS);
0247         /* there might be handshake issue with hardware which needs delay */
0248         mdelay(20);
0249         /* Wait for response flag (bit 31) */
0250         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0251                    0x80000000, 0x80000000, false);
0252     }
0253
0254     return ret;
0255 }
0256
0257 static int psp_v13_0_4_ring_create(struct psp_context *psp,
0258                  enum psp_ring_type ring_type)
0259 {
0260     int ret = 0;
0261     unsigned int psp_ring_reg = 0;
0262     struct psp_ring *ring = &psp->km_ring;
0263     struct amdgpu_device *adev = psp->adev;
0264
0265     if (amdgpu_sriov_vf(adev)) {
0266         ret = psp_v13_0_4_ring_stop(psp, ring_type);
0267         if (ret) {
0268             DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
0269             return ret;
0270         }
0271
0272         /* Write low address of the ring to C2PMSG_102 */
0273         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0274         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
0275         /* Write high address of the ring to C2PMSG_103 */
0276         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0277         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
0278
0279         /* Write the ring initialization command to C2PMSG_101 */
0280         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
0281                  GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
0282
0283         /* there might be handshake issue with hardware which needs delay */
0284         mdelay(20);
0285
0286         /* Wait for response flag (bit 31) in C2PMSG_101 */
0287         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
0288                    0x80000000, 0x8000FFFF, false);
0289
0290     } else {
0291         /* Wait for sOS ready for ring creation */
0292         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0293                    0x80000000, 0x80000000, false);
0294         if (ret) {
0295             DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
0296             return ret;
0297         }
0298
0299         /* Write low address of the ring to C2PMSG_69 */
0300         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0301         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
0302         /* Write high address of the ring to C2PMSG_70 */
0303         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0304         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
0305         /* Write size of ring to C2PMSG_71 */
0306         psp_ring_reg = ring->ring_size;
0307         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
0308         /* Write the ring initialization command to C2PMSG_64 */
0309         psp_ring_reg = ring_type;
0310         psp_ring_reg = psp_ring_reg << 16;
0311         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
0312
0313         /* there might be handshake issue with hardware which needs delay */
0314         mdelay(20);
0315
0316         /* Wait for response flag (bit 31) in C2PMSG_64 */
0317         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0318                    0x80000000, 0x8000FFFF, false);
0319     }
0320
0321     return ret;
0322 }
0323
0324 static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
0325                   enum psp_ring_type ring_type)
0326 {
0327     int ret = 0;
0328     struct psp_ring *ring = &psp->km_ring;
0329     struct amdgpu_device *adev = psp->adev;
0330
0331     ret = psp_v13_0_4_ring_stop(psp, ring_type);
0332     if (ret)
0333         DRM_ERROR("Fail to stop psp ring\n");
0334
0335     amdgpu_bo_free_kernel(&adev->firmware.rbuf,
0336                   &ring->ring_mem_mc_addr,
0337                   (void **)&ring->ring_mem);
0338
0339     return ret;
0340 }
0341
0342 static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
0343 {
0344     uint32_t data;
0345     struct amdgpu_device *adev = psp->adev;
0346
0347     if (amdgpu_sriov_vf(adev))
0348         data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
0349     else
0350         data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
0351
0352     return data;
0353 }
0354
0355 static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
0356 {
0357     struct amdgpu_device *adev = psp->adev;
0358
0359     if (amdgpu_sriov_vf(adev)) {
0360         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
0361         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
0362                  GFX_CTRL_CMD_ID_CONSUME_CMD);
0363     } else
0364         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
0365 }
0366
0367 static const struct psp_funcs psp_v13_0_4_funcs = {
0368     .init_microcode = psp_v13_0_4_init_microcode,
0369     .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
0370     .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
0371     .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
0372     .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
0373     .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
0374     .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
0375     .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
0376     .ring_init = psp_v13_0_4_ring_init,
0377     .ring_create = psp_v13_0_4_ring_create,
0378     .ring_stop = psp_v13_0_4_ring_stop,
0379     .ring_destroy = psp_v13_0_4_ring_destroy,
0380     .ring_get_wptr = psp_v13_0_4_ring_get_wptr,
0381     .ring_set_wptr = psp_v13_0_4_ring_set_wptr,
0382 };
0383
0384 void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
0385 {
0386     psp->funcs = &psp_v13_0_4_funcs;
0387 }