amd/amdgpu/psp_v13_0.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <drm/drm_drv.h>
0024 #include <linux/vmalloc.h>
0025 #include "amdgpu.h"
0026 #include "amdgpu_psp.h"
0027 #include "amdgpu_ucode.h"
0028 #include "soc15_common.h"
0029 #include "psp_v13_0.h"
0030
0031 #include "mp/mp_13_0_2_offset.h"
0032 #include "mp/mp_13_0_2_sh_mask.h"
0033
0034 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
0035 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
0036 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
0037 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
0038 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
0039 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
0040 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
0041 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
0042 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
0043 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
0044 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
0045 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
0046 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
0047
0048 /* For large FW files the time to complete can be very long */
0049 #define USBC_PD_POLLING_LIMIT_S 240
0050
0051 /* Read USB-PD from LFB */
0052 #define GFX_CMD_USB_PD_USE_LFB 0x480
0053
0054 /* VBIOS gfl defines */
0055 #define MBOX_READY_MASK 0x80000000
0056 #define MBOX_STATUS_MASK 0x0000FFFF
0057 #define MBOX_COMMAND_MASK 0x00FF0000
0058 #define MBOX_READY_FLAG 0x80000000
0059 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
0060 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
0061 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
0062
0063 /* memory training timeout define */
0064 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
0065
0066 static int psp_v13_0_init_microcode(struct psp_context *psp)
0067 {
0068     struct amdgpu_device *adev = psp->adev;
0069     const char *chip_name;
0070     char ucode_prefix[30];
0071     int err = 0;
0072
0073     switch (adev->ip_versions[MP0_HWIP][0]) {
0074     case IP_VERSION(13, 0, 2):
0075         chip_name = "aldebaran";
0076         break;
0077     case IP_VERSION(13, 0, 1):
0078     case IP_VERSION(13, 0, 3):
0079         chip_name = "yellow_carp";
0080         break;
0081     default:
0082         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
0083         chip_name = ucode_prefix;
0084         break;
0085     }
0086
0087     switch (adev->ip_versions[MP0_HWIP][0]) {
0088     case IP_VERSION(13, 0, 2):
0089         err = psp_init_sos_microcode(psp, chip_name);
0090         if (err)
0091             return err;
0092         /* It's not necessary to load ras ta on Guest side */
0093         if (!amdgpu_sriov_vf(adev)) {
0094             err = psp_init_ta_microcode(&adev->psp, chip_name);
0095             if (err)
0096                 return err;
0097         }
0098         break;
0099     case IP_VERSION(13, 0, 1):
0100     case IP_VERSION(13, 0, 3):
0101     case IP_VERSION(13, 0, 5):
0102     case IP_VERSION(13, 0, 8):
0103         err = psp_init_toc_microcode(psp, chip_name);
0104         if (err)
0105             return err;
0106         err = psp_init_ta_microcode(psp, chip_name);
0107         if (err)
0108             return err;
0109         break;
0110     case IP_VERSION(13, 0, 0):
0111     case IP_VERSION(13, 0, 7):
0112         err = psp_init_sos_microcode(psp, chip_name);
0113         if (err)
0114             return err;
0115         /* It's not necessary to load ras ta on Guest side */
0116         err = psp_init_ta_microcode(psp, chip_name);
0117         if (err)
0118             return err;
0119         break;
0120     default:
0121         BUG();
0122     }
0123
0124     return 0;
0125 }
0126
0127 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
0128 {
0129     struct amdgpu_device *adev = psp->adev;
0130     uint32_t sol_reg;
0131
0132     sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
0133
0134     return sol_reg != 0x0;
0135 }
0136
0137 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
0138 {
0139     struct amdgpu_device *adev = psp->adev;
0140
0141     int ret;
0142     int retry_loop;
0143
0144     for (retry_loop = 0; retry_loop < 10; retry_loop++) {
0145         /* Wait for bootloader to signify that is
0146             ready having bit 31 of C2PMSG_35 set to 1 */
0147         ret = psp_wait_for(psp,
0148                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0149                    0x80000000,
0150                    0x80000000,
0151                    false);
0152
0153         if (ret == 0)
0154             return 0;
0155     }
0156
0157     return ret;
0158 }
0159
0160 static int psp_v13_0_bootloader_load_component(struct psp_context   *psp,
0161                            struct psp_bin_desc  *bin_desc,
0162                            enum psp_bootloader_cmd  bl_cmd)
0163 {
0164     int ret;
0165     uint32_t psp_gfxdrv_command_reg = 0;
0166     struct amdgpu_device *adev = psp->adev;
0167
0168     /* Check tOS sign of life register to confirm sys driver and sOS
0169      * are already been loaded.
0170      */
0171     if (psp_v13_0_is_sos_alive(psp))
0172         return 0;
0173
0174     ret = psp_v13_0_wait_for_bootloader(psp);
0175     if (ret)
0176         return ret;
0177
0178     memset(psp->fw_pri_buf, 0, PSP_1_MEG);
0179
0180     /* Copy PSP KDB binary to memory */
0181     memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
0182
0183     /* Provide the PSP KDB to bootloader */
0184     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
0185            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0186     psp_gfxdrv_command_reg = bl_cmd;
0187     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
0188            psp_gfxdrv_command_reg);
0189
0190     ret = psp_v13_0_wait_for_bootloader(psp);
0191
0192     return ret;
0193 }
0194
0195 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
0196 {
0197     return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
0198 }
0199
0200 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
0201 {
0202     return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
0203 }
0204
0205 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
0206 {
0207     return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
0208 }
0209
0210 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
0211 {
0212     return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
0213 }
0214
0215 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
0216 {
0217     return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
0218 }
0219
0220 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
0221 {
0222     return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
0223 }
0224
0225 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
0226 {
0227     int ret;
0228     unsigned int psp_gfxdrv_command_reg = 0;
0229     struct amdgpu_device *adev = psp->adev;
0230
0231     /* Check sOS sign of life register to confirm sys driver and sOS
0232      * are already been loaded.
0233      */
0234     if (psp_v13_0_is_sos_alive(psp))
0235         return 0;
0236
0237     ret = psp_v13_0_wait_for_bootloader(psp);
0238     if (ret)
0239         return ret;
0240
0241     memset(psp->fw_pri_buf, 0, PSP_1_MEG);
0242
0243     /* Copy Secure OS binary to PSP memory */
0244     memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
0245
0246     /* Provide the PSP secure OS to bootloader */
0247     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
0248            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0249     psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
0250     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
0251            psp_gfxdrv_command_reg);
0252
0253     /* there might be handshake issue with hardware which needs delay */
0254     mdelay(20);
0255     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
0256                RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
0257                0, true);
0258
0259     return ret;
0260 }
0261
0262 static int psp_v13_0_ring_init(struct psp_context *psp,
0263                   enum psp_ring_type ring_type)
0264 {
0265     int ret = 0;
0266     struct psp_ring *ring;
0267     struct amdgpu_device *adev = psp->adev;
0268
0269     ring = &psp->km_ring;
0270
0271     ring->ring_type = ring_type;
0272
0273     /* allocate 4k Page of Local Frame Buffer memory for ring */
0274     ring->ring_size = 0x1000;
0275     ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
0276                       AMDGPU_GEM_DOMAIN_VRAM,
0277                       &adev->firmware.rbuf,
0278                       &ring->ring_mem_mc_addr,
0279                       (void **)&ring->ring_mem);
0280     if (ret) {
0281         ring->ring_size = 0;
0282         return ret;
0283     }
0284
0285     return 0;
0286 }
0287
0288 static int psp_v13_0_ring_stop(struct psp_context *psp,
0289                    enum psp_ring_type ring_type)
0290 {
0291     int ret = 0;
0292     struct amdgpu_device *adev = psp->adev;
0293
0294     if (amdgpu_sriov_vf(adev)) {
0295         /* Write the ring destroy command*/
0296         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
0297                  GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
0298         /* there might be handshake issue with hardware which needs delay */
0299         mdelay(20);
0300         /* Wait for response flag (bit 31) */
0301         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
0302                    0x80000000, 0x80000000, false);
0303     } else {
0304         /* Write the ring destroy command*/
0305         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
0306                  GFX_CTRL_CMD_ID_DESTROY_RINGS);
0307         /* there might be handshake issue with hardware which needs delay */
0308         mdelay(20);
0309         /* Wait for response flag (bit 31) */
0310         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0311                    0x80000000, 0x80000000, false);
0312     }
0313
0314     return ret;
0315 }
0316
0317 static int psp_v13_0_ring_create(struct psp_context *psp,
0318                  enum psp_ring_type ring_type)
0319 {
0320     int ret = 0;
0321     unsigned int psp_ring_reg = 0;
0322     struct psp_ring *ring = &psp->km_ring;
0323     struct amdgpu_device *adev = psp->adev;
0324
0325     if (amdgpu_sriov_vf(adev)) {
0326         ret = psp_v13_0_ring_stop(psp, ring_type);
0327         if (ret) {
0328             DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
0329             return ret;
0330         }
0331
0332         /* Write low address of the ring to C2PMSG_102 */
0333         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0334         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
0335         /* Write high address of the ring to C2PMSG_103 */
0336         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0337         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
0338
0339         /* Write the ring initialization command to C2PMSG_101 */
0340         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
0341                  GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
0342
0343         /* there might be handshake issue with hardware which needs delay */
0344         mdelay(20);
0345
0346         /* Wait for response flag (bit 31) in C2PMSG_101 */
0347         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
0348                    0x80000000, 0x8000FFFF, false);
0349
0350     } else {
0351         /* Wait for sOS ready for ring creation */
0352         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0353                    0x80000000, 0x80000000, false);
0354         if (ret) {
0355             DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
0356             return ret;
0357         }
0358
0359         /* Write low address of the ring to C2PMSG_69 */
0360         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0361         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
0362         /* Write high address of the ring to C2PMSG_70 */
0363         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0364         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
0365         /* Write size of ring to C2PMSG_71 */
0366         psp_ring_reg = ring->ring_size;
0367         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
0368         /* Write the ring initialization command to C2PMSG_64 */
0369         psp_ring_reg = ring_type;
0370         psp_ring_reg = psp_ring_reg << 16;
0371         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
0372
0373         /* there might be handshake issue with hardware which needs delay */
0374         mdelay(20);
0375
0376         /* Wait for response flag (bit 31) in C2PMSG_64 */
0377         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0378                    0x80000000, 0x8000FFFF, false);
0379     }
0380
0381     return ret;
0382 }
0383
0384 static int psp_v13_0_ring_destroy(struct psp_context *psp,
0385                   enum psp_ring_type ring_type)
0386 {
0387     int ret = 0;
0388     struct psp_ring *ring = &psp->km_ring;
0389     struct amdgpu_device *adev = psp->adev;
0390
0391     ret = psp_v13_0_ring_stop(psp, ring_type);
0392     if (ret)
0393         DRM_ERROR("Fail to stop psp ring\n");
0394
0395     amdgpu_bo_free_kernel(&adev->firmware.rbuf,
0396                   &ring->ring_mem_mc_addr,
0397                   (void **)&ring->ring_mem);
0398
0399     return ret;
0400 }
0401
0402 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
0403 {
0404     uint32_t data;
0405     struct amdgpu_device *adev = psp->adev;
0406
0407     if (amdgpu_sriov_vf(adev))
0408         data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
0409     else
0410         data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
0411
0412     return data;
0413 }
0414
0415 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
0416 {
0417     struct amdgpu_device *adev = psp->adev;
0418
0419     if (amdgpu_sriov_vf(adev)) {
0420         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
0421         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
0422                  GFX_CTRL_CMD_ID_CONSUME_CMD);
0423     } else
0424         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
0425 }
0426
0427 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
0428 {
0429     int ret;
0430     int i;
0431     uint32_t data_32;
0432     int max_wait;
0433     struct amdgpu_device *adev = psp->adev;
0434
0435     data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
0436     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
0437     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
0438
0439     max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
0440     for (i = 0; i < max_wait; i++) {
0441         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0442                    0x80000000, 0x80000000, false);
0443         if (ret == 0)
0444             break;
0445     }
0446     if (i < max_wait)
0447         ret = 0;
0448     else
0449         ret = -ETIME;
0450
0451     dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
0452           (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
0453           (ret == 0) ? "succeed" : "failed",
0454           i, adev->usec_timeout/1000);
0455     return ret;
0456 }
0457
0458
0459 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
0460 {
0461     struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
0462     uint32_t *pcache = (uint32_t *)ctx->sys_cache;
0463     struct amdgpu_device *adev = psp->adev;
0464     uint32_t p2c_header[4];
0465     uint32_t sz;
0466     void *buf;
0467     int ret, idx;
0468
0469     if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
0470         dev_dbg(adev->dev, "Memory training is not supported.\n");
0471         return 0;
0472     } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
0473         dev_err(adev->dev, "Memory training initialization failure.\n");
0474         return -EINVAL;
0475     }
0476
0477     if (psp_v13_0_is_sos_alive(psp)) {
0478         dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
0479         return 0;
0480     }
0481
0482     amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
0483     dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
0484           pcache[0], pcache[1], pcache[2], pcache[3],
0485           p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
0486
0487     if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
0488         dev_dbg(adev->dev, "Short training depends on restore.\n");
0489         ops |= PSP_MEM_TRAIN_RESTORE;
0490     }
0491
0492     if ((ops & PSP_MEM_TRAIN_RESTORE) &&
0493         pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
0494         dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
0495         ops |= PSP_MEM_TRAIN_SAVE;
0496     }
0497
0498     if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
0499         !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
0500           pcache[3] == p2c_header[3])) {
0501         dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
0502         ops |= PSP_MEM_TRAIN_SAVE;
0503     }
0504
0505     if ((ops & PSP_MEM_TRAIN_SAVE) &&
0506         p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
0507         dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
0508         ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
0509     }
0510
0511     if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
0512         ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
0513         ops |= PSP_MEM_TRAIN_SAVE;
0514     }
0515
0516     dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
0517
0518     if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
0519         /*
0520          * Long training will encroach a certain amount on the bottom of VRAM;
0521          * save the content from the bottom of VRAM to system memory
0522          * before training, and restore it after training to avoid
0523          * VRAM corruption.
0524          */
0525         sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
0526
0527         if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
0528             dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
0529                   adev->gmc.visible_vram_size,
0530                   adev->mman.aper_base_kaddr);
0531             return -EINVAL;
0532         }
0533
0534         buf = vmalloc(sz);
0535         if (!buf) {
0536             dev_err(adev->dev, "failed to allocate system memory.\n");
0537             return -ENOMEM;
0538         }
0539
0540         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
0541             memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
0542             ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
0543             if (ret) {
0544                 DRM_ERROR("Send long training msg failed.\n");
0545                 vfree(buf);
0546                 drm_dev_exit(idx);
0547                 return ret;
0548             }
0549
0550             memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
0551             adev->hdp.funcs->flush_hdp(adev, NULL);
0552             vfree(buf);
0553             drm_dev_exit(idx);
0554         } else {
0555             vfree(buf);
0556             return -ENODEV;
0557         }
0558     }
0559
0560     if (ops & PSP_MEM_TRAIN_SAVE) {
0561         amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
0562     }
0563
0564     if (ops & PSP_MEM_TRAIN_RESTORE) {
0565         amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
0566     }
0567
0568     if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
0569         ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
0570                              PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
0571         if (ret) {
0572             dev_err(adev->dev, "send training msg failed.\n");
0573             return ret;
0574         }
0575     }
0576     ctx->training_cnt++;
0577     return 0;
0578 }
0579
0580 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
0581 {
0582     struct amdgpu_device *adev = psp->adev;
0583     uint32_t reg_status;
0584     int ret, i = 0;
0585
0586     /*
0587      * LFB address which is aligned to 1MB address and has to be
0588      * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
0589      * register
0590      */
0591     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
0592
0593     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0594                  0x80000000, 0x80000000, false);
0595     if (ret)
0596         return ret;
0597
0598     /* Fireup interrupt so PSP can pick up the address */
0599     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
0600
0601     /* FW load takes very long time */
0602     do {
0603         msleep(1000);
0604         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
0605
0606         if (reg_status & 0x80000000)
0607             goto done;
0608
0609     } while (++i < USBC_PD_POLLING_LIMIT_S);
0610
0611     return -ETIME;
0612 done:
0613
0614     if ((reg_status & 0xFFFF) != 0) {
0615         DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
0616                 reg_status & 0xFFFF);
0617         return -EIO;
0618     }
0619
0620     return 0;
0621 }
0622
0623 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
0624 {
0625     struct amdgpu_device *adev = psp->adev;
0626     int ret;
0627
0628     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
0629
0630     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0631                      0x80000000, 0x80000000, false);
0632     if (!ret)
0633         *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
0634
0635     return ret;
0636 }
0637
0638 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
0639 {
0640     uint32_t reg_status = 0, reg_val = 0;
0641     struct amdgpu_device *adev = psp->adev;
0642     int ret;
0643
0644     /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
0645     reg_val |= (cmd << 16);
0646     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
0647
0648     /* Ring the doorbell */
0649     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
0650
0651     if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
0652         return 0;
0653
0654     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
0655                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
0656     if (ret) {
0657         dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
0658         return ret;
0659     }
0660
0661     reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
0662     if ((reg_status & 0xFFFF) != 0) {
0663         dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
0664                 cmd, reg_status & 0xFFFF);
0665         return -EIO;
0666     }
0667
0668     return 0;
0669 }
0670
0671 static int psp_v13_0_update_spirom(struct psp_context *psp,
0672                    uint64_t fw_pri_mc_addr)
0673 {
0674     struct amdgpu_device *adev = psp->adev;
0675     int ret;
0676
0677     /* Confirm PSP is ready to start */
0678     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
0679                MBOX_READY_FLAG, MBOX_READY_MASK, false);
0680     if (ret) {
0681         dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
0682         return ret;
0683     }
0684
0685     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
0686
0687     ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
0688     if (ret)
0689         return ret;
0690
0691     WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
0692
0693     ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
0694     if (ret)
0695         return ret;
0696
0697     psp->vbflash_done = true;
0698
0699     ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
0700     if (ret)
0701         return ret;
0702
0703     return 0;
0704 }
0705
0706 static int psp_v13_0_vbflash_status(struct psp_context *psp)
0707 {
0708     struct amdgpu_device *adev = psp->adev;
0709
0710     return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
0711 }
0712
0713 static const struct psp_funcs psp_v13_0_funcs = {
0714     .init_microcode = psp_v13_0_init_microcode,
0715     .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
0716     .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
0717     .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
0718     .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
0719     .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
0720     .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
0721     .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
0722     .ring_init = psp_v13_0_ring_init,
0723     .ring_create = psp_v13_0_ring_create,
0724     .ring_stop = psp_v13_0_ring_stop,
0725     .ring_destroy = psp_v13_0_ring_destroy,
0726     .ring_get_wptr = psp_v13_0_ring_get_wptr,
0727     .ring_set_wptr = psp_v13_0_ring_set_wptr,
0728     .mem_training = psp_v13_0_memory_training,
0729     .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
0730     .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
0731     .update_spirom = psp_v13_0_update_spirom,
0732     .vbflash_stat = psp_v13_0_vbflash_status
0733 };
0734
0735 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
0736 {
0737     psp->funcs = &psp_v13_0_funcs;
0738 }