amd/amdgpu/psp_v12_0.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #include <linux/firmware.h>
0024 #include <linux/module.h>
0025 #include "amdgpu.h"
0026 #include "amdgpu_psp.h"
0027 #include "amdgpu_ucode.h"
0028 #include "soc15_common.h"
0029 #include "psp_v12_0.h"
0030
0031 #include "mp/mp_12_0_0_offset.h"
0032 #include "mp/mp_12_0_0_sh_mask.h"
0033 #include "gc/gc_9_0_offset.h"
0034 #include "sdma0/sdma0_4_0_offset.h"
0035 #include "nbio/nbio_7_4_offset.h"
0036
0037 #include "oss/osssys_4_0_offset.h"
0038 #include "oss/osssys_4_0_sh_mask.h"
0039
0040 MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
0041 MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
0042 MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
0043 MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
0044
0045 /* address block */
0046 #define smnMP1_FIRMWARE_FLAGS       0x3010024
0047
0048 static int psp_v12_0_init_microcode(struct psp_context *psp)
0049 {
0050     struct amdgpu_device *adev = psp->adev;
0051     const char *chip_name;
0052     char fw_name[30];
0053     int err = 0;
0054     const struct ta_firmware_header_v1_0 *ta_hdr;
0055     DRM_DEBUG("\n");
0056
0057     switch (adev->asic_type) {
0058     case CHIP_RENOIR:
0059         if (adev->apu_flags & AMD_APU_IS_RENOIR)
0060             chip_name = "renoir";
0061         else
0062             chip_name = "green_sardine";
0063         break;
0064     default:
0065         BUG();
0066     }
0067
0068     err = psp_init_asd_microcode(psp, chip_name);
0069     if (err)
0070         return err;
0071
0072     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
0073     err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
0074     if (err) {
0075         release_firmware(adev->psp.ta_fw);
0076         adev->psp.ta_fw = NULL;
0077         dev_info(adev->dev,
0078              "psp v12.0: Failed to load firmware \"%s\"\n",
0079              fw_name);
0080     } else {
0081         err = amdgpu_ucode_validate(adev->psp.ta_fw);
0082         if (err)
0083             goto out;
0084
0085         ta_hdr = (const struct ta_firmware_header_v1_0 *)
0086                  adev->psp.ta_fw->data;
0087         adev->psp.hdcp_context.context.bin_desc.fw_version =
0088             le32_to_cpu(ta_hdr->hdcp.fw_version);
0089         adev->psp.hdcp_context.context.bin_desc.size_bytes =
0090             le32_to_cpu(ta_hdr->hdcp.size_bytes);
0091         adev->psp.hdcp_context.context.bin_desc.start_addr =
0092             (uint8_t *)ta_hdr +
0093             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
0094
0095         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
0096
0097         adev->psp.dtm_context.context.bin_desc.fw_version =
0098             le32_to_cpu(ta_hdr->dtm.fw_version);
0099         adev->psp.dtm_context.context.bin_desc.size_bytes =
0100             le32_to_cpu(ta_hdr->dtm.size_bytes);
0101         adev->psp.dtm_context.context.bin_desc.start_addr =
0102             (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
0103             le32_to_cpu(ta_hdr->dtm.offset_bytes);
0104
0105         if (adev->apu_flags & AMD_APU_IS_RENOIR) {
0106             adev->psp.securedisplay_context.context.bin_desc.fw_version =
0107                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
0108             adev->psp.securedisplay_context.context.bin_desc.size_bytes =
0109                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
0110             adev->psp.securedisplay_context.context.bin_desc.start_addr =
0111                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
0112                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
0113         }
0114     }
0115
0116     return 0;
0117
0118 out:
0119     release_firmware(adev->psp.ta_fw);
0120     adev->psp.ta_fw = NULL;
0121     if (err) {
0122         dev_err(adev->dev,
0123             "psp v12.0: Failed to load firmware \"%s\"\n",
0124             fw_name);
0125     }
0126
0127     return err;
0128 }
0129
0130 static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
0131 {
0132     int ret;
0133     uint32_t psp_gfxdrv_command_reg = 0;
0134     struct amdgpu_device *adev = psp->adev;
0135     uint32_t sol_reg;
0136
0137     /* Check sOS sign of life register to confirm sys driver and sOS
0138      * are already been loaded.
0139      */
0140     sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
0141     if (sol_reg)
0142         return 0;
0143
0144     /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
0145     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0146                0x80000000, 0x80000000, false);
0147     if (ret)
0148         return ret;
0149
0150     /* Copy PSP System Driver binary to memory */
0151     psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
0152
0153     /* Provide the sys driver to bootloader */
0154     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
0155            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0156     psp_gfxdrv_command_reg = 1 << 16;
0157     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
0158            psp_gfxdrv_command_reg);
0159
0160     /* there might be handshake issue with hardware which needs delay */
0161     mdelay(20);
0162
0163     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0164                0x80000000, 0x80000000, false);
0165
0166     return ret;
0167 }
0168
0169 static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
0170 {
0171     int ret;
0172     unsigned int psp_gfxdrv_command_reg = 0;
0173     struct amdgpu_device *adev = psp->adev;
0174     uint32_t sol_reg;
0175
0176     /* Check sOS sign of life register to confirm sys driver and sOS
0177      * are already been loaded.
0178      */
0179     sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
0180     if (sol_reg)
0181         return 0;
0182
0183     /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
0184     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0185                0x80000000, 0x80000000, false);
0186     if (ret)
0187         return ret;
0188
0189     /* Copy Secure OS binary to PSP memory */
0190     psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
0191
0192     /* Provide the PSP secure OS to bootloader */
0193     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
0194            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0195     psp_gfxdrv_command_reg = 2 << 16;
0196     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
0197            psp_gfxdrv_command_reg);
0198
0199     /* there might be handshake issue with hardware which needs delay */
0200     mdelay(20);
0201     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
0202                RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
0203                0, true);
0204
0205     return ret;
0206 }
0207
0208 static void psp_v12_0_reroute_ih(struct psp_context *psp)
0209 {
0210     struct amdgpu_device *adev = psp->adev;
0211     uint32_t tmp;
0212
0213     /* Change IH ring for VMC */
0214     tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
0215     tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
0216     tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
0217
0218     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
0219     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
0220     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
0221
0222     mdelay(20);
0223     psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0224              0x80000000, 0x8000FFFF, false);
0225
0226     /* Change IH ring for UMC */
0227     tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
0228     tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
0229
0230     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
0231     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
0232     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
0233
0234     mdelay(20);
0235     psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0236              0x80000000, 0x8000FFFF, false);
0237 }
0238
0239 static int psp_v12_0_ring_init(struct psp_context *psp,
0240                   enum psp_ring_type ring_type)
0241 {
0242     int ret = 0;
0243     struct psp_ring *ring;
0244     struct amdgpu_device *adev = psp->adev;
0245
0246     psp_v12_0_reroute_ih(psp);
0247
0248     ring = &psp->km_ring;
0249
0250     ring->ring_type = ring_type;
0251
0252     /* allocate 4k Page of Local Frame Buffer memory for ring */
0253     ring->ring_size = 0x1000;
0254     ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
0255                       AMDGPU_GEM_DOMAIN_VRAM,
0256                       &adev->firmware.rbuf,
0257                       &ring->ring_mem_mc_addr,
0258                       (void **)&ring->ring_mem);
0259     if (ret) {
0260         ring->ring_size = 0;
0261         return ret;
0262     }
0263
0264     return 0;
0265 }
0266
0267 static int psp_v12_0_ring_create(struct psp_context *psp,
0268                 enum psp_ring_type ring_type)
0269 {
0270     int ret = 0;
0271     unsigned int psp_ring_reg = 0;
0272     struct psp_ring *ring = &psp->km_ring;
0273     struct amdgpu_device *adev = psp->adev;
0274
0275     if (amdgpu_sriov_vf(psp->adev)) {
0276         /* Write low address of the ring to C2PMSG_102 */
0277         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0278         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
0279         /* Write high address of the ring to C2PMSG_103 */
0280         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0281         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
0282
0283         /* Write the ring initialization command to C2PMSG_101 */
0284         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0285                          GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
0286
0287         /* there might be handshake issue with hardware which needs delay */
0288         mdelay(20);
0289
0290         /* Wait for response flag (bit 31) in C2PMSG_101 */
0291         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0292                    0x80000000, 0x8000FFFF, false);
0293
0294     } else {
0295         /* Write low address of the ring to C2PMSG_69 */
0296         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0297         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
0298         /* Write high address of the ring to C2PMSG_70 */
0299         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0300         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
0301         /* Write size of ring to C2PMSG_71 */
0302         psp_ring_reg = ring->ring_size;
0303         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
0304         /* Write the ring initialization command to C2PMSG_64 */
0305         psp_ring_reg = ring_type;
0306         psp_ring_reg = psp_ring_reg << 16;
0307         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
0308
0309         /* there might be handshake issue with hardware which needs delay */
0310         mdelay(20);
0311
0312         /* Wait for response flag (bit 31) in C2PMSG_64 */
0313         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0314                    0x80000000, 0x8000FFFF, false);
0315     }
0316
0317     return ret;
0318 }
0319
0320 static int psp_v12_0_ring_stop(struct psp_context *psp,
0321                   enum psp_ring_type ring_type)
0322 {
0323     int ret = 0;
0324     struct amdgpu_device *adev = psp->adev;
0325
0326     /* Write the ring destroy command*/
0327     if (amdgpu_sriov_vf(adev))
0328         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0329                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
0330     else
0331         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
0332                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
0333
0334     /* there might be handshake issue with hardware which needs delay */
0335     mdelay(20);
0336
0337     /* Wait for response flag (bit 31) */
0338     if (amdgpu_sriov_vf(adev))
0339         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0340                    0x80000000, 0x80000000, false);
0341     else
0342         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0343                    0x80000000, 0x80000000, false);
0344
0345     return ret;
0346 }
0347
0348 static int psp_v12_0_ring_destroy(struct psp_context *psp,
0349                  enum psp_ring_type ring_type)
0350 {
0351     int ret = 0;
0352     struct psp_ring *ring = &psp->km_ring;
0353     struct amdgpu_device *adev = psp->adev;
0354
0355     ret = psp_v12_0_ring_stop(psp, ring_type);
0356     if (ret)
0357         DRM_ERROR("Fail to stop psp ring\n");
0358
0359     amdgpu_bo_free_kernel(&adev->firmware.rbuf,
0360                   &ring->ring_mem_mc_addr,
0361                   (void **)&ring->ring_mem);
0362
0363     return ret;
0364 }
0365
0366 static int psp_v12_0_mode1_reset(struct psp_context *psp)
0367 {
0368     int ret;
0369     uint32_t offset;
0370     struct amdgpu_device *adev = psp->adev;
0371
0372     offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
0373
0374     ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
0375
0376     if (ret) {
0377         DRM_INFO("psp is not working correctly before mode1 reset!\n");
0378         return -EINVAL;
0379     }
0380
0381     /*send the mode 1 reset command*/
0382     WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
0383
0384     msleep(500);
0385
0386     offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
0387
0388     ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
0389
0390     if (ret) {
0391         DRM_INFO("psp mode 1 reset failed!\n");
0392         return -EINVAL;
0393     }
0394
0395     DRM_INFO("psp mode1 reset succeed \n");
0396
0397     return 0;
0398 }
0399
0400 static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
0401 {
0402     uint32_t data;
0403     struct amdgpu_device *adev = psp->adev;
0404
0405     if (amdgpu_sriov_vf(adev))
0406         data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
0407     else
0408         data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
0409
0410     return data;
0411 }
0412
0413 static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
0414 {
0415     struct amdgpu_device *adev = psp->adev;
0416
0417     if (amdgpu_sriov_vf(adev)) {
0418         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
0419         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
0420     } else
0421         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
0422 }
0423
0424 static const struct psp_funcs psp_v12_0_funcs = {
0425     .init_microcode = psp_v12_0_init_microcode,
0426     .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
0427     .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
0428     .ring_init = psp_v12_0_ring_init,
0429     .ring_create = psp_v12_0_ring_create,
0430     .ring_stop = psp_v12_0_ring_stop,
0431     .ring_destroy = psp_v12_0_ring_destroy,
0432     .mode1_reset = psp_v12_0_mode1_reset,
0433     .ring_get_wptr = psp_v12_0_ring_get_wptr,
0434     .ring_set_wptr = psp_v12_0_ring_set_wptr,
0435 };
0436
0437 void psp_v12_0_set_psp_funcs(struct psp_context *psp)
0438 {
0439     psp->funcs = &psp_v12_0_funcs;
0440 }