amd/amdgpu/psp_v11_0_8.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "amdgpu_psp.h"
0025 #include "amdgpu_ucode.h"
0026 #include "soc15_common.h"
0027 #include "psp_v11_0_8.h"
0028
0029 #include "mp/mp_11_0_8_offset.h"
0030
0031 static int psp_v11_0_8_ring_init(struct psp_context *psp,
0032                   enum psp_ring_type ring_type)
0033 {
0034     int ret = 0;
0035     struct psp_ring *ring;
0036     struct amdgpu_device *adev = psp->adev;
0037
0038     ring = &psp->km_ring;
0039
0040     ring->ring_type = ring_type;
0041
0042     /* allocate 4k Page of Local Frame Buffer memory for ring */
0043     ring->ring_size = 0x1000;
0044     ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
0045                       AMDGPU_GEM_DOMAIN_VRAM,
0046                       &adev->firmware.rbuf,
0047                       &ring->ring_mem_mc_addr,
0048                       (void **)&ring->ring_mem);
0049     if (ret) {
0050         ring->ring_size = 0;
0051         return ret;
0052     }
0053
0054     return 0;
0055 }
0056
0057 static int psp_v11_0_8_ring_stop(struct psp_context *psp,
0058                    enum psp_ring_type ring_type)
0059 {
0060     int ret = 0;
0061     struct amdgpu_device *adev = psp->adev;
0062
0063     if (amdgpu_sriov_vf(adev)) {
0064         /* Write the ring destroy command*/
0065         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0066                  GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
0067         /* there might be handshake issue with hardware which needs delay */
0068         mdelay(20);
0069         /* Wait for response flag (bit 31) */
0070         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0071                    0x80000000, 0x80000000, false);
0072     } else {
0073         /* Write the ring destroy command*/
0074         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
0075                  GFX_CTRL_CMD_ID_DESTROY_RINGS);
0076         /* there might be handshake issue with hardware which needs delay */
0077         mdelay(20);
0078         /* Wait for response flag (bit 31) */
0079         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0080                    0x80000000, 0x80000000, false);
0081     }
0082
0083     return ret;
0084 }
0085
0086 static int psp_v11_0_8_ring_create(struct psp_context *psp,
0087                  enum psp_ring_type ring_type)
0088 {
0089     int ret = 0;
0090     unsigned int psp_ring_reg = 0;
0091     struct psp_ring *ring = &psp->km_ring;
0092     struct amdgpu_device *adev = psp->adev;
0093
0094     if (amdgpu_sriov_vf(adev)) {
0095         ret = psp_v11_0_8_ring_stop(psp, ring_type);
0096         if (ret) {
0097             DRM_ERROR("psp_v11_0_8_ring_stop_sriov failed!\n");
0098             return ret;
0099         }
0100
0101         /* Write low address of the ring to C2PMSG_102 */
0102         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0103         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
0104         /* Write high address of the ring to C2PMSG_103 */
0105         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0106         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
0107
0108         /* Write the ring initialization command to C2PMSG_101 */
0109         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0110                  GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
0111
0112         /* there might be handshake issue with hardware which needs delay */
0113         mdelay(20);
0114
0115         /* Wait for response flag (bit 31) in C2PMSG_101 */
0116         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0117                    0x80000000, 0x8000FFFF, false);
0118
0119     } else {
0120         /* Wait for sOS ready for ring creation */
0121         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0122                    0x80000000, 0x80000000, false);
0123         if (ret) {
0124             DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
0125             return ret;
0126         }
0127
0128         /* Write low address of the ring to C2PMSG_69 */
0129         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0130         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
0131         /* Write high address of the ring to C2PMSG_70 */
0132         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0133         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
0134         /* Write size of ring to C2PMSG_71 */
0135         psp_ring_reg = ring->ring_size;
0136         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
0137         /* Write the ring initialization command to C2PMSG_64 */
0138         psp_ring_reg = ring_type;
0139         psp_ring_reg = psp_ring_reg << 16;
0140         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
0141
0142         /* there might be handshake issue with hardware which needs delay */
0143         mdelay(20);
0144
0145         /* Wait for response flag (bit 31) in C2PMSG_64 */
0146         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0147                    0x80000000, 0x8000FFFF, false);
0148     }
0149
0150     return ret;
0151 }
0152
0153 static int psp_v11_0_8_ring_destroy(struct psp_context *psp,
0154                   enum psp_ring_type ring_type)
0155 {
0156     int ret = 0;
0157     struct psp_ring *ring = &psp->km_ring;
0158     struct amdgpu_device *adev = psp->adev;
0159
0160     ret = psp_v11_0_8_ring_stop(psp, ring_type);
0161     if (ret)
0162         DRM_ERROR("Fail to stop psp ring\n");
0163
0164     amdgpu_bo_free_kernel(&adev->firmware.rbuf,
0165                   &ring->ring_mem_mc_addr,
0166                   (void **)&ring->ring_mem);
0167
0168     return ret;
0169 }
0170
0171 static uint32_t psp_v11_0_8_ring_get_wptr(struct psp_context *psp)
0172 {
0173     uint32_t data;
0174     struct amdgpu_device *adev = psp->adev;
0175
0176     if (amdgpu_sriov_vf(adev))
0177         data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
0178     else
0179         data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
0180
0181     return data;
0182 }
0183
0184 static void psp_v11_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)
0185 {
0186     struct amdgpu_device *adev = psp->adev;
0187
0188     if (amdgpu_sriov_vf(adev)) {
0189         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
0190         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0191                  GFX_CTRL_CMD_ID_CONSUME_CMD);
0192     } else
0193         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
0194 }
0195
0196 static const struct psp_funcs psp_v11_0_8_funcs = {
0197     .ring_init = psp_v11_0_8_ring_init,
0198     .ring_create = psp_v11_0_8_ring_create,
0199     .ring_stop = psp_v11_0_8_ring_stop,
0200     .ring_destroy = psp_v11_0_8_ring_destroy,
0201     .ring_get_wptr = psp_v11_0_8_ring_get_wptr,
0202     .ring_set_wptr = psp_v11_0_8_ring_set_wptr,
0203 };
0204
0205 void psp_v11_0_8_set_psp_funcs(struct psp_context *psp)
0206 {
0207     psp->funcs = &psp_v11_0_8_funcs;
0208 }