Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 
0023 #include <linux/firmware.h>
0024 #include <linux/module.h>
0025 #include <linux/vmalloc.h>
0026 #include <drm/drm_drv.h>
0027 
0028 #include "amdgpu.h"
0029 #include "amdgpu_psp.h"
0030 #include "amdgpu_ras.h"
0031 #include "amdgpu_ucode.h"
0032 #include "soc15_common.h"
0033 #include "psp_v11_0.h"
0034 
0035 #include "mp/mp_11_0_offset.h"
0036 #include "mp/mp_11_0_sh_mask.h"
0037 #include "gc/gc_9_0_offset.h"
0038 #include "sdma0/sdma0_4_0_offset.h"
0039 #include "nbio/nbio_7_4_offset.h"
0040 
0041 #include "oss/osssys_4_0_offset.h"
0042 #include "oss/osssys_4_0_sh_mask.h"
0043 
0044 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
0045 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
0046 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
0047 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
0048 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
0049 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
0050 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
0051 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
0052 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
0053 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
0054 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
0055 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
0056 MODULE_FIRMWARE("amdgpu/navi12_cap.bin");
0057 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
0058 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
0059 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
0060 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
0061 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
0062 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin");
0063 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
0064 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
0065 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
0066 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
0067 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
0068 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
0069 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
0070 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");
0071 
0072 /* address block */
0073 #define smnMP1_FIRMWARE_FLAGS       0x3010024
0074 /* navi10 reg offset define */
0075 #define mmRLC_GPM_UCODE_ADDR_NV10   0x5b61
0076 #define mmRLC_GPM_UCODE_DATA_NV10   0x5b62
0077 #define mmSDMA0_UCODE_ADDR_NV10     0x5880
0078 #define mmSDMA0_UCODE_DATA_NV10     0x5881
0079 /* memory training timeout define */
0080 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
0081 
0082 /* For large FW files the time to complete can be very long */
0083 #define USBC_PD_POLLING_LIMIT_S 240
0084 
0085 /* Read USB-PD from LFB */
0086 #define GFX_CMD_USB_PD_USE_LFB 0x480
0087 
0088 static int psp_v11_0_init_microcode(struct psp_context *psp)
0089 {
0090     struct amdgpu_device *adev = psp->adev;
0091     const char *chip_name;
0092     char fw_name[PSP_FW_NAME_LEN];
0093     int err = 0;
0094     const struct ta_firmware_header_v1_0 *ta_hdr;
0095 
0096     DRM_DEBUG("\n");
0097 
0098     switch (adev->ip_versions[MP0_HWIP][0]) {
0099     case IP_VERSION(11, 0, 2):
0100         chip_name = "vega20";
0101         break;
0102     case IP_VERSION(11, 0, 0):
0103         chip_name = "navi10";
0104         break;
0105     case IP_VERSION(11, 0, 5):
0106         chip_name = "navi14";
0107         break;
0108     case IP_VERSION(11, 0, 9):
0109         chip_name = "navi12";
0110         break;
0111     case IP_VERSION(11, 0, 4):
0112         chip_name = "arcturus";
0113         break;
0114     case IP_VERSION(11, 0, 7):
0115         chip_name = "sienna_cichlid";
0116         break;
0117     case IP_VERSION(11, 0, 11):
0118         chip_name = "navy_flounder";
0119         break;
0120     case IP_VERSION(11, 5, 0):
0121         chip_name = "vangogh";
0122         break;
0123     case IP_VERSION(11, 0, 12):
0124         chip_name = "dimgrey_cavefish";
0125         break;
0126     case IP_VERSION(11, 0, 13):
0127         chip_name = "beige_goby";
0128         break;
0129     default:
0130         BUG();
0131     }
0132 
0133 
0134     switch (adev->ip_versions[MP0_HWIP][0]) {
0135     case IP_VERSION(11, 0, 2):
0136     case IP_VERSION(11, 0, 4):
0137         err = psp_init_sos_microcode(psp, chip_name);
0138         if (err)
0139             return err;
0140         err = psp_init_asd_microcode(psp, chip_name);
0141         if (err)
0142             return err;
0143         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
0144         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
0145         if (err) {
0146             release_firmware(adev->psp.ta_fw);
0147             adev->psp.ta_fw = NULL;
0148             dev_info(adev->dev,
0149                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
0150         } else {
0151             err = amdgpu_ucode_validate(adev->psp.ta_fw);
0152             if (err)
0153                 goto out2;
0154 
0155             ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
0156             adev->psp.xgmi_context.context.bin_desc.fw_version =
0157                 le32_to_cpu(ta_hdr->xgmi.fw_version);
0158             adev->psp.xgmi_context.context.bin_desc.size_bytes =
0159                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
0160             adev->psp.xgmi_context.context.bin_desc.start_addr =
0161                 (uint8_t *)ta_hdr +
0162                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
0163             adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
0164             adev->psp.ras_context.context.bin_desc.fw_version =
0165                 le32_to_cpu(ta_hdr->ras.fw_version);
0166             adev->psp.ras_context.context.bin_desc.size_bytes =
0167                 le32_to_cpu(ta_hdr->ras.size_bytes);
0168             adev->psp.ras_context.context.bin_desc.start_addr =
0169                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
0170                 le32_to_cpu(ta_hdr->ras.offset_bytes);
0171         }
0172         break;
0173     case IP_VERSION(11, 0, 0):
0174     case IP_VERSION(11, 0, 5):
0175     case IP_VERSION(11, 0, 9):
0176         err = psp_init_sos_microcode(psp, chip_name);
0177         if (err)
0178             return err;
0179         err = psp_init_asd_microcode(psp, chip_name);
0180         if (err)
0181             return err;
0182         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
0183         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
0184         if (err) {
0185             release_firmware(adev->psp.ta_fw);
0186             adev->psp.ta_fw = NULL;
0187             dev_info(adev->dev,
0188                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
0189         } else {
0190             err = amdgpu_ucode_validate(adev->psp.ta_fw);
0191             if (err)
0192                 goto out2;
0193 
0194             ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
0195             adev->psp.hdcp_context.context.bin_desc.fw_version =
0196                 le32_to_cpu(ta_hdr->hdcp.fw_version);
0197             adev->psp.hdcp_context.context.bin_desc.size_bytes =
0198                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
0199             adev->psp.hdcp_context.context.bin_desc.start_addr =
0200                 (uint8_t *)ta_hdr +
0201                 le32_to_cpu(
0202                     ta_hdr->header.ucode_array_offset_bytes);
0203 
0204             adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
0205 
0206             adev->psp.dtm_context.context.bin_desc.fw_version =
0207                 le32_to_cpu(ta_hdr->dtm.fw_version);
0208             adev->psp.dtm_context.context.bin_desc.size_bytes =
0209                 le32_to_cpu(ta_hdr->dtm.size_bytes);
0210             adev->psp.dtm_context.context.bin_desc.start_addr =
0211                 (uint8_t *)adev->psp.hdcp_context.context
0212                     .bin_desc.start_addr +
0213                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
0214         }
0215         break;
0216     case IP_VERSION(11, 0, 7):
0217     case IP_VERSION(11, 0, 11):
0218     case IP_VERSION(11, 0, 12):
0219     case IP_VERSION(11, 0, 13):
0220         err = psp_init_sos_microcode(psp, chip_name);
0221         if (err)
0222             return err;
0223         err = psp_init_ta_microcode(psp, chip_name);
0224         if (err)
0225             return err;
0226         break;
0227     case IP_VERSION(11, 5, 0):
0228         err = psp_init_asd_microcode(psp, chip_name);
0229         if (err)
0230             return err;
0231         err = psp_init_toc_microcode(psp, chip_name);
0232         if (err)
0233             return err;
0234         break;
0235     default:
0236         BUG();
0237     }
0238 
0239     return 0;
0240 
0241 out2:
0242     release_firmware(adev->psp.ta_fw);
0243     adev->psp.ta_fw = NULL;
0244     return err;
0245 }
0246 
0247 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
0248 {
0249     struct amdgpu_device *adev = psp->adev;
0250 
0251     int ret;
0252     int retry_loop;
0253 
0254     for (retry_loop = 0; retry_loop < 10; retry_loop++) {
0255         /* Wait for bootloader to signify that is
0256             ready having bit 31 of C2PMSG_35 set to 1 */
0257         ret = psp_wait_for(psp,
0258                    SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0259                    0x80000000,
0260                    0x80000000,
0261                    false);
0262 
0263         if (ret == 0)
0264             return 0;
0265     }
0266 
0267     return ret;
0268 }
0269 
0270 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
0271 {
0272     struct amdgpu_device *adev = psp->adev;
0273     uint32_t sol_reg;
0274 
0275     sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
0276 
0277     return sol_reg != 0x0;
0278 }
0279 
0280 static int psp_v11_0_bootloader_load_component(struct psp_context   *psp,
0281                            struct psp_bin_desc  *bin_desc,
0282                            enum psp_bootloader_cmd  bl_cmd)
0283 {
0284     int ret;
0285     uint32_t psp_gfxdrv_command_reg = 0;
0286     struct amdgpu_device *adev = psp->adev;
0287 
0288     /* Check sOS sign of life register to confirm sys driver and sOS
0289      * are already been loaded.
0290      */
0291     if (psp_v11_0_is_sos_alive(psp))
0292         return 0;
0293 
0294     ret = psp_v11_0_wait_for_bootloader(psp);
0295     if (ret)
0296         return ret;
0297 
0298     /* Copy PSP System Driver binary to memory */
0299     psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);
0300 
0301     /* Provide the sys driver to bootloader */
0302     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
0303            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0304     psp_gfxdrv_command_reg = bl_cmd;
0305     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
0306            psp_gfxdrv_command_reg);
0307 
0308     ret = psp_v11_0_wait_for_bootloader(psp);
0309 
0310     return ret;
0311 }
0312 
0313 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
0314 {
0315     return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
0316 }
0317 
0318 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
0319 {
0320     return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
0321 }
0322 
0323 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
0324 {
0325     return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
0326 }
0327 
0328 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
0329 {
0330     int ret;
0331     unsigned int psp_gfxdrv_command_reg = 0;
0332     struct amdgpu_device *adev = psp->adev;
0333 
0334     /* Check sOS sign of life register to confirm sys driver and sOS
0335      * are already been loaded.
0336      */
0337     if (psp_v11_0_is_sos_alive(psp))
0338         return 0;
0339 
0340     ret = psp_v11_0_wait_for_bootloader(psp);
0341     if (ret)
0342         return ret;
0343 
0344     /* Copy Secure OS binary to PSP memory */
0345     psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
0346 
0347     /* Provide the PSP secure OS to bootloader */
0348     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
0349            (uint32_t)(psp->fw_pri_mc_addr >> 20));
0350     psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
0351     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
0352            psp_gfxdrv_command_reg);
0353 
0354     /* there might be handshake issue with hardware which needs delay */
0355     mdelay(20);
0356     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
0357                RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
0358                0, true);
0359 
0360     return ret;
0361 }
0362 
0363 static int psp_v11_0_ring_init(struct psp_context *psp,
0364                   enum psp_ring_type ring_type)
0365 {
0366     int ret = 0;
0367     struct psp_ring *ring;
0368     struct amdgpu_device *adev = psp->adev;
0369 
0370     ring = &psp->km_ring;
0371 
0372     ring->ring_type = ring_type;
0373 
0374     /* allocate 4k Page of Local Frame Buffer memory for ring */
0375     ring->ring_size = 0x1000;
0376     ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
0377                       AMDGPU_GEM_DOMAIN_VRAM,
0378                       &adev->firmware.rbuf,
0379                       &ring->ring_mem_mc_addr,
0380                       (void **)&ring->ring_mem);
0381     if (ret) {
0382         ring->ring_size = 0;
0383         return ret;
0384     }
0385 
0386     return 0;
0387 }
0388 
0389 static int psp_v11_0_ring_stop(struct psp_context *psp,
0390                   enum psp_ring_type ring_type)
0391 {
0392     int ret = 0;
0393     struct amdgpu_device *adev = psp->adev;
0394 
0395     /* Write the ring destroy command*/
0396     if (amdgpu_sriov_vf(adev))
0397         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0398                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
0399     else
0400         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
0401                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
0402 
0403     /* there might be handshake issue with hardware which needs delay */
0404     mdelay(20);
0405 
0406     /* Wait for response flag (bit 31) */
0407     if (amdgpu_sriov_vf(adev))
0408         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0409                    0x80000000, 0x80000000, false);
0410     else
0411         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0412                    0x80000000, 0x80000000, false);
0413 
0414     return ret;
0415 }
0416 
0417 static int psp_v11_0_ring_create(struct psp_context *psp,
0418                 enum psp_ring_type ring_type)
0419 {
0420     int ret = 0;
0421     unsigned int psp_ring_reg = 0;
0422     struct psp_ring *ring = &psp->km_ring;
0423     struct amdgpu_device *adev = psp->adev;
0424 
0425     if (amdgpu_sriov_vf(adev)) {
0426         ring->ring_wptr = 0;
0427         ret = psp_v11_0_ring_stop(psp, ring_type);
0428         if (ret) {
0429             DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
0430             return ret;
0431         }
0432 
0433         /* Write low address of the ring to C2PMSG_102 */
0434         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0435         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
0436         /* Write high address of the ring to C2PMSG_103 */
0437         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0438         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
0439 
0440         /* Write the ring initialization command to C2PMSG_101 */
0441         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
0442                          GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
0443 
0444         /* there might be handshake issue with hardware which needs delay */
0445         mdelay(20);
0446 
0447         /* Wait for response flag (bit 31) in C2PMSG_101 */
0448         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0449                    0x80000000, 0x8000FFFF, false);
0450 
0451     } else {
0452         /* Wait for sOS ready for ring creation */
0453         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0454                    0x80000000, 0x80000000, false);
0455         if (ret) {
0456             DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
0457             return ret;
0458         }
0459 
0460         /* Write low address of the ring to C2PMSG_69 */
0461         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0462         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
0463         /* Write high address of the ring to C2PMSG_70 */
0464         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0465         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
0466         /* Write size of ring to C2PMSG_71 */
0467         psp_ring_reg = ring->ring_size;
0468         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
0469         /* Write the ring initialization command to C2PMSG_64 */
0470         psp_ring_reg = ring_type;
0471         psp_ring_reg = psp_ring_reg << 16;
0472         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
0473 
0474         /* there might be handshake issue with hardware which needs delay */
0475         mdelay(20);
0476 
0477         /* Wait for response flag (bit 31) in C2PMSG_64 */
0478         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0479                    0x80000000, 0x8000FFFF, false);
0480     }
0481 
0482     return ret;
0483 }
0484 
0485 
0486 static int psp_v11_0_ring_destroy(struct psp_context *psp,
0487                  enum psp_ring_type ring_type)
0488 {
0489     int ret = 0;
0490     struct psp_ring *ring = &psp->km_ring;
0491     struct amdgpu_device *adev = psp->adev;
0492 
0493     ret = psp_v11_0_ring_stop(psp, ring_type);
0494     if (ret)
0495         DRM_ERROR("Fail to stop psp ring\n");
0496 
0497     amdgpu_bo_free_kernel(&adev->firmware.rbuf,
0498                   &ring->ring_mem_mc_addr,
0499                   (void **)&ring->ring_mem);
0500 
0501     return ret;
0502 }
0503 
0504 static int psp_v11_0_mode1_reset(struct psp_context *psp)
0505 {
0506     int ret;
0507     uint32_t offset;
0508     struct amdgpu_device *adev = psp->adev;
0509 
0510     offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
0511 
0512     ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
0513 
0514     if (ret) {
0515         DRM_INFO("psp is not working correctly before mode1 reset!\n");
0516         return -EINVAL;
0517     }
0518 
0519     /*send the mode 1 reset command*/
0520     WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
0521 
0522     msleep(500);
0523 
0524     offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
0525 
0526     ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
0527 
0528     if (ret) {
0529         DRM_INFO("psp mode 1 reset failed!\n");
0530         return -EINVAL;
0531     }
0532 
0533     DRM_INFO("psp mode1 reset succeed \n");
0534 
0535     return 0;
0536 }
0537 
0538 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
0539 {
0540     int ret;
0541     int i;
0542     uint32_t data_32;
0543     int max_wait;
0544     struct amdgpu_device *adev = psp->adev;
0545 
0546     data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
0547     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
0548     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
0549 
0550     max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
0551     for (i = 0; i < max_wait; i++) {
0552         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0553                    0x80000000, 0x80000000, false);
0554         if (ret == 0)
0555             break;
0556     }
0557     if (i < max_wait)
0558         ret = 0;
0559     else
0560         ret = -ETIME;
0561 
0562     DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
0563           (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
0564           (ret == 0) ? "succeed" : "failed",
0565           i, adev->usec_timeout/1000);
0566     return ret;
0567 }
0568 
0569 /*
0570  * save and restore process
0571  */
0572 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
0573 {
0574     struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
0575     uint32_t *pcache = (uint32_t *)ctx->sys_cache;
0576     struct amdgpu_device *adev = psp->adev;
0577     uint32_t p2c_header[4];
0578     uint32_t sz;
0579     void *buf;
0580     int ret, idx;
0581 
0582     if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
0583         DRM_DEBUG("Memory training is not supported.\n");
0584         return 0;
0585     } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
0586         DRM_ERROR("Memory training initialization failure.\n");
0587         return -EINVAL;
0588     }
0589 
0590     if (psp_v11_0_is_sos_alive(psp)) {
0591         DRM_DEBUG("SOS is alive, skip memory training.\n");
0592         return 0;
0593     }
0594 
0595     amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
0596     DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
0597           pcache[0], pcache[1], pcache[2], pcache[3],
0598           p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
0599 
0600     if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
0601         DRM_DEBUG("Short training depends on restore.\n");
0602         ops |= PSP_MEM_TRAIN_RESTORE;
0603     }
0604 
0605     if ((ops & PSP_MEM_TRAIN_RESTORE) &&
0606         pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
0607         DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
0608         ops |= PSP_MEM_TRAIN_SAVE;
0609     }
0610 
0611     if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
0612         !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
0613           pcache[3] == p2c_header[3])) {
0614         DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
0615         ops |= PSP_MEM_TRAIN_SAVE;
0616     }
0617 
0618     if ((ops & PSP_MEM_TRAIN_SAVE) &&
0619         p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
0620         DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
0621         ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
0622     }
0623 
0624     if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
0625         ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
0626         ops |= PSP_MEM_TRAIN_SAVE;
0627     }
0628 
0629     DRM_DEBUG("Memory training ops:%x.\n", ops);
0630 
0631     if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
0632         /*
0633          * Long training will encroach a certain amount on the bottom of VRAM;
0634          * save the content from the bottom of VRAM to system memory
0635          * before training, and restore it after training to avoid
0636          * VRAM corruption.
0637          */
0638         sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
0639 
0640         if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
0641             DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
0642                   adev->gmc.visible_vram_size,
0643                   adev->mman.aper_base_kaddr);
0644             return -EINVAL;
0645         }
0646 
0647         buf = vmalloc(sz);
0648         if (!buf) {
0649             DRM_ERROR("failed to allocate system memory.\n");
0650             return -ENOMEM;
0651         }
0652 
0653         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
0654             memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
0655             ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
0656             if (ret) {
0657                 DRM_ERROR("Send long training msg failed.\n");
0658                 vfree(buf);
0659                 drm_dev_exit(idx);
0660                 return ret;
0661             }
0662 
0663             memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
0664             adev->hdp.funcs->flush_hdp(adev, NULL);
0665             vfree(buf);
0666             drm_dev_exit(idx);
0667         } else {
0668             vfree(buf);
0669             return -ENODEV;
0670         }
0671     }
0672 
0673     if (ops & PSP_MEM_TRAIN_SAVE) {
0674         amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
0675     }
0676 
0677     if (ops & PSP_MEM_TRAIN_RESTORE) {
0678         amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
0679     }
0680 
0681     if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
0682         ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
0683                              PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
0684         if (ret) {
0685             DRM_ERROR("send training msg failed.\n");
0686             return ret;
0687         }
0688     }
0689     ctx->training_cnt++;
0690     return 0;
0691 }
0692 
0693 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
0694 {
0695     uint32_t data;
0696     struct amdgpu_device *adev = psp->adev;
0697 
0698     if (amdgpu_sriov_vf(adev))
0699         data = psp->km_ring.ring_wptr;
0700     else
0701         data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
0702 
0703     return data;
0704 }
0705 
0706 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
0707 {
0708     struct amdgpu_device *adev = psp->adev;
0709 
0710     if (amdgpu_sriov_vf(adev)) {
0711         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
0712         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
0713         psp->km_ring.ring_wptr = value;
0714     } else
0715         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
0716 }
0717 
0718 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
0719 {
0720     struct amdgpu_device *adev = psp->adev;
0721     uint32_t reg_status;
0722     int ret, i = 0;
0723 
0724     /*
0725      * LFB address which is aligned to 1MB address and has to be
0726      * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
0727      * register
0728      */
0729     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
0730 
0731     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0732                  0x80000000, 0x80000000, false);
0733     if (ret)
0734         return ret;
0735 
0736     /* Fireup interrupt so PSP can pick up the address */
0737     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
0738 
0739     /* FW load takes very long time */
0740     do {
0741         msleep(1000);
0742         reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
0743 
0744         if (reg_status & 0x80000000)
0745             goto done;
0746 
0747     } while (++i < USBC_PD_POLLING_LIMIT_S);
0748 
0749     return -ETIME;
0750 done:
0751 
0752     if ((reg_status & 0xFFFF) != 0) {
0753         DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n",
0754                 reg_status & 0xFFFF);
0755         return -EIO;
0756     }
0757 
0758     return 0;
0759 }
0760 
0761 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
0762 {
0763     struct amdgpu_device *adev = psp->adev;
0764     int ret;
0765 
0766     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
0767 
0768     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0769                      0x80000000, 0x80000000, false);
0770     if (!ret)
0771         *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
0772 
0773     return ret;
0774 }
0775 
0776 static const struct psp_funcs psp_v11_0_funcs = {
0777     .init_microcode = psp_v11_0_init_microcode,
0778     .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
0779     .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
0780     .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
0781     .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
0782     .ring_init = psp_v11_0_ring_init,
0783     .ring_create = psp_v11_0_ring_create,
0784     .ring_stop = psp_v11_0_ring_stop,
0785     .ring_destroy = psp_v11_0_ring_destroy,
0786     .mode1_reset = psp_v11_0_mode1_reset,
0787     .mem_training = psp_v11_0_memory_training,
0788     .ring_get_wptr = psp_v11_0_ring_get_wptr,
0789     .ring_set_wptr = psp_v11_0_ring_set_wptr,
0790     .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
0791     .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
0792 };
0793 
0794 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
0795 {
0796     psp->funcs = &psp_v11_0_funcs;
0797 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!