amd/amdgpu/psp_v10_0.c

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Author: Huang Rui
0023  *
0024  */
0025
0026 #include <linux/firmware.h>
0027 #include <linux/module.h>
0028 #include <linux/pci.h>
0029
0030 #include "amdgpu.h"
0031 #include "amdgpu_psp.h"
0032 #include "amdgpu_ucode.h"
0033 #include "soc15_common.h"
0034 #include "psp_v10_0.h"
0035
0036 #include "mp/mp_10_0_offset.h"
0037 #include "gc/gc_9_1_offset.h"
0038 #include "sdma0/sdma0_4_1_offset.h"
0039
0040 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
0041 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
0042 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
0043 MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
0044 MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
0045 MODULE_FIRMWARE("amdgpu/raven_ta.bin");
0046
0047 static int psp_v10_0_init_microcode(struct psp_context *psp)
0048 {
0049     struct amdgpu_device *adev = psp->adev;
0050     const char *chip_name;
0051     char fw_name[30];
0052     int err = 0;
0053     const struct ta_firmware_header_v1_0 *ta_hdr;
0054     DRM_DEBUG("\n");
0055
0056     switch (adev->asic_type) {
0057     case CHIP_RAVEN:
0058         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
0059             chip_name = "raven2";
0060         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
0061             chip_name = "picasso";
0062         else
0063             chip_name = "raven";
0064         break;
0065     default: BUG();
0066     }
0067
0068     err = psp_init_asd_microcode(psp, chip_name);
0069     if (err)
0070         goto out;
0071
0072     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
0073     err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
0074     if (err) {
0075         release_firmware(adev->psp.ta_fw);
0076         adev->psp.ta_fw = NULL;
0077         dev_info(adev->dev,
0078              "psp v10.0: Failed to load firmware \"%s\"\n",
0079              fw_name);
0080     } else {
0081         err = amdgpu_ucode_validate(adev->psp.ta_fw);
0082         if (err)
0083             goto out2;
0084
0085         ta_hdr = (const struct ta_firmware_header_v1_0 *)
0086                  adev->psp.ta_fw->data;
0087         adev->psp.hdcp_context.context.bin_desc.fw_version =
0088             le32_to_cpu(ta_hdr->hdcp.fw_version);
0089         adev->psp.hdcp_context.context.bin_desc.size_bytes =
0090             le32_to_cpu(ta_hdr->hdcp.size_bytes);
0091         adev->psp.hdcp_context.context.bin_desc.start_addr =
0092             (uint8_t *)ta_hdr +
0093             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
0094
0095         adev->psp.dtm_context.context.bin_desc.fw_version =
0096             le32_to_cpu(ta_hdr->dtm.fw_version);
0097         adev->psp.dtm_context.context.bin_desc.size_bytes =
0098             le32_to_cpu(ta_hdr->dtm.size_bytes);
0099         adev->psp.dtm_context.context.bin_desc.start_addr =
0100             (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
0101             le32_to_cpu(ta_hdr->dtm.offset_bytes);
0102
0103         adev->psp.securedisplay_context.context.bin_desc.fw_version =
0104             le32_to_cpu(ta_hdr->securedisplay.fw_version);
0105         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
0106             le32_to_cpu(ta_hdr->securedisplay.size_bytes);
0107         adev->psp.securedisplay_context.context.bin_desc.start_addr =
0108             (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
0109             le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
0110
0111         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
0112     }
0113
0114     return 0;
0115
0116 out2:
0117     release_firmware(adev->psp.ta_fw);
0118     adev->psp.ta_fw = NULL;
0119 out:
0120     if (err) {
0121         dev_err(adev->dev,
0122             "psp v10.0: Failed to load firmware \"%s\"\n",
0123             fw_name);
0124     }
0125
0126     return err;
0127 }
0128
0129 static int psp_v10_0_ring_init(struct psp_context *psp,
0130                    enum psp_ring_type ring_type)
0131 {
0132     int ret = 0;
0133     struct psp_ring *ring;
0134     struct amdgpu_device *adev = psp->adev;
0135
0136     ring = &psp->km_ring;
0137
0138     ring->ring_type = ring_type;
0139
0140     /* allocate 4k Page of Local Frame Buffer memory for ring */
0141     ring->ring_size = 0x1000;
0142     ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
0143                       AMDGPU_GEM_DOMAIN_VRAM,
0144                       &adev->firmware.rbuf,
0145                       &ring->ring_mem_mc_addr,
0146                       (void **)&ring->ring_mem);
0147     if (ret) {
0148         ring->ring_size = 0;
0149         return ret;
0150     }
0151
0152     return 0;
0153 }
0154
0155 static int psp_v10_0_ring_create(struct psp_context *psp,
0156                  enum psp_ring_type ring_type)
0157 {
0158     int ret = 0;
0159     unsigned int psp_ring_reg = 0;
0160     struct psp_ring *ring = &psp->km_ring;
0161     struct amdgpu_device *adev = psp->adev;
0162
0163     /* Write low address of the ring to C2PMSG_69 */
0164     psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
0165     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
0166     /* Write high address of the ring to C2PMSG_70 */
0167     psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
0168     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
0169     /* Write size of ring to C2PMSG_71 */
0170     psp_ring_reg = ring->ring_size;
0171     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
0172     /* Write the ring initialization command to C2PMSG_64 */
0173     psp_ring_reg = ring_type;
0174     psp_ring_reg = psp_ring_reg << 16;
0175     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
0176
0177     /* There might be handshake issue with hardware which needs delay */
0178     mdelay(20);
0179
0180     /* Wait for response flag (bit 31) in C2PMSG_64 */
0181     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0182                0x80000000, 0x8000FFFF, false);
0183
0184     return ret;
0185 }
0186
0187 static int psp_v10_0_ring_stop(struct psp_context *psp,
0188                    enum psp_ring_type ring_type)
0189 {
0190     int ret = 0;
0191     unsigned int psp_ring_reg = 0;
0192     struct amdgpu_device *adev = psp->adev;
0193
0194     /* Write the ring destroy command to C2PMSG_64 */
0195     psp_ring_reg = 3 << 16;
0196     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
0197
0198     /* There might be handshake issue with hardware which needs delay */
0199     mdelay(20);
0200
0201     /* Wait for response flag (bit 31) in C2PMSG_64 */
0202     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0203                0x80000000, 0x80000000, false);
0204
0205     return ret;
0206 }
0207
0208 static int psp_v10_0_ring_destroy(struct psp_context *psp,
0209                   enum psp_ring_type ring_type)
0210 {
0211     int ret = 0;
0212     struct psp_ring *ring = &psp->km_ring;
0213     struct amdgpu_device *adev = psp->adev;
0214
0215     ret = psp_v10_0_ring_stop(psp, ring_type);
0216     if (ret)
0217         DRM_ERROR("Fail to stop psp ring\n");
0218
0219     amdgpu_bo_free_kernel(&adev->firmware.rbuf,
0220                   &ring->ring_mem_mc_addr,
0221                   (void **)&ring->ring_mem);
0222
0223     return ret;
0224 }
0225
0226 static int psp_v10_0_mode1_reset(struct psp_context *psp)
0227 {
0228     DRM_INFO("psp mode 1 reset not supported now! \n");
0229     return -EINVAL;
0230 }
0231
0232 static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
0233 {
0234     struct amdgpu_device *adev = psp->adev;
0235
0236     return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
0237 }
0238
0239 static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
0240 {
0241     struct amdgpu_device *adev = psp->adev;
0242
0243     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
0244 }
0245
0246 static const struct psp_funcs psp_v10_0_funcs = {
0247     .init_microcode = psp_v10_0_init_microcode,
0248     .ring_init = psp_v10_0_ring_init,
0249     .ring_create = psp_v10_0_ring_create,
0250     .ring_stop = psp_v10_0_ring_stop,
0251     .ring_destroy = psp_v10_0_ring_destroy,
0252     .mode1_reset = psp_v10_0_mode1_reset,
0253     .ring_get_wptr = psp_v10_0_ring_get_wptr,
0254     .ring_set_wptr = psp_v10_0_ring_set_wptr,
0255 };
0256
0257 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
0258 {
0259     psp->funcs = &psp_v10_0_funcs;
0260 }