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0001 /* 0002 * Copyright 2017 Advanced Micro Devices, Inc. 0003 * 0004 * Permission is hereby granted, free of charge, to any person obtaining a 0005 * copy of this software and associated documentation files (the "Software"), 0006 * to deal in the Software without restriction, including without limitation 0007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 0008 * and/or sell copies of the Software, and to permit persons to whom the 0009 * Software is furnished to do so, subject to the following conditions: 0010 * 0011 * The above copyright notice and this permission notice shall be included in 0012 * all copies or substantial portions of the Software. 0013 * 0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 0017 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 0018 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 0019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 0020 * OTHER DEALINGS IN THE SOFTWARE. 0021 * 0022 */ 0023 0024 #ifndef _PSP_TEE_GFX_IF_H_ 0025 #define _PSP_TEE_GFX_IF_H_ 0026 0027 #define PSP_GFX_CMD_BUF_VERSION 0x00000001 0028 0029 #define GFX_CMD_STATUS_MASK 0x0000FFFF 0030 #define GFX_CMD_ID_MASK 0x000F0000 0031 #define GFX_CMD_RESERVED_MASK 0x7FF00000 0032 #define GFX_CMD_RESPONSE_MASK 0x80000000 0033 0034 /* USBC PD FW version retrieval command */ 0035 #define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000 0036 0037 /* TEE Gfx Command IDs for the register interface. 0038 * Command ID must be between 0x00010000 and 0x000F0000. 0039 */ 0040 enum psp_gfx_crtl_cmd_id 0041 { 0042 GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ 0043 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ 0044 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ 0045 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ 0046 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */ 0047 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */ 0048 GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */ 0049 GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */ 0050 GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to psp for updating write pointer of vf */ 0051 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */ 0052 0053 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ 0054 }; 0055 0056 0057 /*----------------------------------------------------------------------------- 0058 NOTE: All physical addresses used in this interface are actually 0059 GPU Virtual Addresses. 0060 */ 0061 0062 0063 /* Control registers of the TEE Gfx interface. These are located in 0064 * SRBM-to-PSP mailbox registers (total 8 registers). 0065 */ 0066 struct psp_gfx_ctrl 0067 { 0068 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */ 0069 volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */ 0070 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */ 0071 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ 0072 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ 0073 volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/ 0074 volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */ 0075 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */ 0076 0077 }; 0078 0079 0080 /* Response flag is set in the command when command is completed by PSP. 0081 * Used in the GFX_CTRL.CmdResp. 0082 * When PSP GFX I/F is initialized, the flag is set. 0083 */ 0084 #define GFX_FLAG_RESPONSE 0x80000000 0085 0086 /* TEE Gfx Command IDs for the ring buffer interface. */ 0087 enum psp_gfx_cmd_id 0088 { 0089 GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ 0090 GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ 0091 GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ 0092 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ 0093 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ 0094 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ 0095 GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */ 0096 GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */ 0097 GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */ 0098 GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */ 0099 GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */ 0100 GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F, /* Query GPUVA of the Fw Attestation DB */ 0101 /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */ 0102 GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */ 0103 GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */ 0104 GFX_CMD_ID_BOOT_CFG = 0x00000022, /* Boot Config */ 0105 }; 0106 0107 /* PSP boot config sub-commands */ 0108 enum psp_gfx_boot_config_cmd 0109 { 0110 BOOTCFG_CMD_SET = 1, /* Set boot configuration settings */ 0111 BOOTCFG_CMD_GET = 2, /* Get boot configuration settings */ 0112 BOOTCFG_CMD_INVALIDATE = 3 /* Reset current boot configuration settings to VBIOS defaults */ 0113 }; 0114 0115 /* PSP boot config bitmask values */ 0116 enum psp_gfx_boot_config 0117 { 0118 BOOT_CONFIG_GECC = 0x1, 0119 }; 0120 0121 /* Command to load Trusted Application binary into PSP OS. */ 0122 struct psp_gfx_cmd_load_ta 0123 { 0124 uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */ 0125 uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */ 0126 uint32_t app_len; /* length of the TA binary in bytes */ 0127 uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */ 0128 uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */ 0129 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ 0130 0131 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided 0132 * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead 0133 * of using global persistent buffer. 0134 */ 0135 }; 0136 0137 0138 /* Command to Unload Trusted Application binary from PSP OS. */ 0139 struct psp_gfx_cmd_unload_ta 0140 { 0141 uint32_t session_id; /* Session ID of the loaded TA to be unloaded */ 0142 0143 }; 0144 0145 0146 /* Shared buffers for InvokeCommand. 0147 */ 0148 struct psp_gfx_buf_desc 0149 { 0150 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */ 0151 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */ 0152 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ 0153 0154 }; 0155 0156 /* Max number of descriptors for one shared buffer (in how many different 0157 * physical locations one shared buffer can be stored). If buffer is too much 0158 * fragmented, error will be returned. 0159 */ 0160 #define GFX_BUF_MAX_DESC 64 0161 0162 struct psp_gfx_buf_list 0163 { 0164 uint32_t num_desc; /* number of buffer descriptors in the list */ 0165 uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ 0166 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ 0167 0168 /* total 776 bytes */ 0169 }; 0170 0171 /* Command to execute InvokeCommand entry point of the TA. */ 0172 struct psp_gfx_cmd_invoke_cmd 0173 { 0174 uint32_t session_id; /* Session ID of the TA to be executed */ 0175 uint32_t ta_cmd_id; /* Command ID to be sent to TA */ 0176 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ 0177 0178 }; 0179 0180 0181 /* Command to setup TMR region. */ 0182 struct psp_gfx_cmd_setup_tmr 0183 { 0184 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */ 0185 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */ 0186 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ 0187 union { 0188 struct { 0189 uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/ 0190 uint32_t virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/ 0191 uint32_t reserved:30; 0192 } bitfield; 0193 uint32_t tmr_flags; 0194 }; 0195 uint32_t system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */ 0196 uint32_t system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffer */ 0197 0198 }; 0199 0200 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ 0201 enum psp_gfx_fw_type { 0202 GFX_FW_TYPE_NONE = 0, /* */ 0203 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */ 0204 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */ 0205 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */ 0206 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */ 0207 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */ 0208 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */ 0209 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */ 0210 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */ 0211 GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */ 0212 GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */ 0213 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */ 0214 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */ 0215 GFX_FW_TYPE_VCN = 13, /* VCN RV */ 0216 GFX_FW_TYPE_UVD = 14, /* UVD VG */ 0217 GFX_FW_TYPE_VCE = 15, /* VCE VG */ 0218 GFX_FW_TYPE_ISP = 16, /* ISP RV */ 0219 GFX_FW_TYPE_ACP = 17, /* ACP RV */ 0220 GFX_FW_TYPE_SMU = 18, /* SMU VG */ 0221 GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */ 0222 GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */ 0223 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */ 0224 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */ 0225 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */ 0226 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */ 0227 GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */ 0228 GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */ 0229 GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */ 0230 GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */ 0231 GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */ 0232 GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */ 0233 GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */ 0234 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */ 0235 GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */ 0236 GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */ 0237 GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */ 0238 GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */ 0239 GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */ 0240 GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */ 0241 GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */ 0242 GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */ 0243 GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */ 0244 GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */ 0245 GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */ 0246 GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */ 0247 GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */ 0248 GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */ 0249 GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */ 0250 GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */ 0251 GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */ 0252 GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */ 0253 GFX_FW_TYPE_DMUB = 51, /* DMUB RN */ 0254 GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */ 0255 GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */ 0256 GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */ 0257 GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */ 0258 GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */ 0259 GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */ 0260 GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */ 0261 GFX_FW_TYPE_CAP = 62, /* CAP_FW */ 0262 GFX_FW_TYPE_SE2_TAP_DELAYS = 65, /* SE2 TAP DELAYS NV */ 0263 GFX_FW_TYPE_SE3_TAP_DELAYS = 66, /* SE3 TAP DELAYS NV */ 0264 GFX_FW_TYPE_REG_LIST = 67, /* REG_LIST MI */ 0265 GFX_FW_TYPE_IMU_I = 68, /* IMU Instruction FW SOC21 */ 0266 GFX_FW_TYPE_IMU_D = 69, /* IMU Data FW SOC21 */ 0267 GFX_FW_TYPE_LSDMA = 70, /* LSDMA FW SOC21 */ 0268 GFX_FW_TYPE_SDMA_UCODE_TH0 = 71, /* SDMA Thread 0/CTX SOC21 */ 0269 GFX_FW_TYPE_SDMA_UCODE_TH1 = 72, /* SDMA Thread 1/CTL SOC21 */ 0270 GFX_FW_TYPE_PPTABLE = 73, /* PPTABLE SOC21 */ 0271 GFX_FW_TYPE_DISCRETE_USB4 = 74, /* dUSB4 FW SOC21 */ 0272 GFX_FW_TYPE_TA = 75, /* SRIOV TA FW UUID SOC21 */ 0273 GFX_FW_TYPE_RS64_MES = 76, /* RS64 MES ucode SOC21 */ 0274 GFX_FW_TYPE_RS64_MES_STACK = 77, /* RS64 MES stack ucode SOC21 */ 0275 GFX_FW_TYPE_RS64_KIQ = 78, /* RS64 KIQ ucode SOC21 */ 0276 GFX_FW_TYPE_RS64_KIQ_STACK = 79, /* RS64 KIQ Heap stack SOC21 */ 0277 GFX_FW_TYPE_ISP_DATA = 80, /* ISP DATA SOC21 */ 0278 GFX_FW_TYPE_CP_MES_KIQ = 81, /* MES KIQ ucode SOC21 */ 0279 GFX_FW_TYPE_MES_KIQ_STACK = 82, /* MES KIQ stack SOC21 */ 0280 GFX_FW_TYPE_UMSCH_DATA = 83, /* User Mode Scheduler Data SOC21 */ 0281 GFX_FW_TYPE_UMSCH_UCODE = 84, /* User Mode Scheduler Ucode SOC21 */ 0282 GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85, /* User Mode Scheduler Command Buffer SOC21 */ 0283 GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */ 0284 GFX_FW_TYPE_RS64_PFP = 87, /* RS64 PFP SOC21 */ 0285 GFX_FW_TYPE_RS64_ME = 88, /* RS64 ME SOC21 */ 0286 GFX_FW_TYPE_RS64_MEC = 89, /* RS64 MEC SOC21 */ 0287 GFX_FW_TYPE_RS64_PFP_P0_STACK = 90, /* RS64 PFP stack P0 SOC21 */ 0288 GFX_FW_TYPE_RS64_PFP_P1_STACK = 91, /* RS64 PFP stack P1 SOC21 */ 0289 GFX_FW_TYPE_RS64_ME_P0_STACK = 92, /* RS64 ME stack P0 SOC21 */ 0290 GFX_FW_TYPE_RS64_ME_P1_STACK = 93, /* RS64 ME stack P1 SOC21 */ 0291 GFX_FW_TYPE_RS64_MEC_P0_STACK = 94, /* RS64 MEC stack P0 SOC21 */ 0292 GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */ 0293 GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */ 0294 GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */ 0295 GFX_FW_TYPE_MAX 0296 }; 0297 0298 /* Command to load HW IP FW. */ 0299 struct psp_gfx_cmd_load_ip_fw 0300 { 0301 uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ 0302 uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ 0303 uint32_t fw_size; /* FW buffer size in bytes */ 0304 enum psp_gfx_fw_type fw_type; /* FW type */ 0305 0306 }; 0307 0308 /* Command to save/restore HW IP FW. */ 0309 struct psp_gfx_cmd_save_restore_ip_fw 0310 { 0311 uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/ 0312 uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */ 0313 uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */ 0314 uint32_t buf_size; /* Size of the save/restore buffer in bytes */ 0315 enum psp_gfx_fw_type fw_type; /* FW type */ 0316 }; 0317 0318 /* Command to setup register program */ 0319 struct psp_gfx_cmd_reg_prog { 0320 uint32_t reg_value; 0321 uint32_t reg_id; 0322 }; 0323 0324 /* Command to load TOC */ 0325 struct psp_gfx_cmd_load_toc 0326 { 0327 uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ 0328 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ 0329 uint32_t toc_size; /* FW buffer size in bytes */ 0330 }; 0331 0332 /* Dynamic boot configuration */ 0333 struct psp_gfx_cmd_boot_cfg 0334 { 0335 uint32_t timestamp; /* calendar time as number of seconds */ 0336 enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process command data */ 0337 uint32_t boot_config; /* dynamic boot configuration bitmask */ 0338 uint32_t boot_config_valid; /* dynamic boot configuration valid bits bitmask */ 0339 }; 0340 0341 /* All GFX ring buffer commands. */ 0342 union psp_gfx_commands 0343 { 0344 struct psp_gfx_cmd_load_ta cmd_load_ta; 0345 struct psp_gfx_cmd_unload_ta cmd_unload_ta; 0346 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; 0347 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; 0348 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; 0349 struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw; 0350 struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog; 0351 struct psp_gfx_cmd_setup_tmr cmd_setup_vmr; 0352 struct psp_gfx_cmd_load_toc cmd_load_toc; 0353 struct psp_gfx_cmd_boot_cfg boot_cfg; 0354 }; 0355 0356 struct psp_gfx_uresp_reserved 0357 { 0358 uint32_t reserved[8]; 0359 }; 0360 0361 /* Command-specific response for Fw Attestation Db */ 0362 struct psp_gfx_uresp_fwar_db_info 0363 { 0364 uint32_t fwar_db_addr_lo; 0365 uint32_t fwar_db_addr_hi; 0366 }; 0367 0368 /* Command-specific response for boot config. */ 0369 struct psp_gfx_uresp_bootcfg { 0370 uint32_t boot_cfg; /* boot config data */ 0371 }; 0372 0373 /* Union of command-specific responses for GPCOM ring. */ 0374 union psp_gfx_uresp { 0375 struct psp_gfx_uresp_reserved reserved; 0376 struct psp_gfx_uresp_bootcfg boot_cfg; 0377 struct psp_gfx_uresp_fwar_db_info fwar_db_info; 0378 }; 0379 0380 /* Structure of GFX Response buffer. 0381 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI 0382 * it is separate buffer. 0383 */ 0384 struct psp_gfx_resp 0385 { 0386 uint32_t status; /* +0 status of command execution */ 0387 uint32_t session_id; /* +4 session ID in response to LoadTa command */ 0388 uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ 0389 uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ 0390 uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */ 0391 0392 uint32_t reserved[11]; 0393 0394 union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */ 0395 0396 /* total 96 bytes */ 0397 }; 0398 0399 /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi 0400 * and psp_gfx_rb_frame.cmd_buf_addr_lo. 0401 */ 0402 struct psp_gfx_cmd_resp 0403 { 0404 uint32_t buf_size; /* +0 total size of the buffer in bytes */ 0405 uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ 0406 uint32_t cmd_id; /* +8 command ID */ 0407 0408 /* These fields are used for RBI only. They are all 0 in GPCOM commands 0409 */ 0410 uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */ 0411 uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */ 0412 uint32_t resp_offset; /* +20 offset within response buffer */ 0413 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */ 0414 0415 union psp_gfx_commands cmd; /* +28 command specific structures */ 0416 0417 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; 0418 0419 /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response 0420 * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. 0421 */ 0422 struct psp_gfx_resp resp; /* +864 response */ 0423 0424 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; 0425 0426 /* total size 1024 bytes */ 0427 }; 0428 0429 0430 #define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ 0431 0432 /* Structure of the Ring Buffer Frame */ 0433 struct psp_gfx_rb_frame 0434 { 0435 uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */ 0436 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */ 0437 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */ 0438 uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */ 0439 uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */ 0440 uint32_t fence_value; /* +20 Fence value */ 0441 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ 0442 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ 0443 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */ 0444 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ 0445 uint8_t reserved1[2]; /* +34 reserved, must be 0 */ 0446 uint32_t reserved2[7]; /* +36 reserved, must be 0 */ 0447 /* total 64 bytes */ 0448 }; 0449 0450 #define PSP_ERR_UNKNOWN_COMMAND 0x00000100 0451 0452 enum tee_error_code { 0453 TEE_SUCCESS = 0x00000000, 0454 TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A, 0455 }; 0456 0457 #endif /* _PSP_TEE_GFX_IF_H_ */
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