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0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/firmware.h>
0024 #include <linux/slab.h>
0025 #include <linux/module.h>
0026 #include <linux/pci.h>
0027 
0028 #include <drm/amdgpu_drm.h>
0029 
0030 #include "amdgpu.h"
0031 #include "amdgpu_atombios.h"
0032 #include "amdgpu_ih.h"
0033 #include "amdgpu_uvd.h"
0034 #include "amdgpu_vce.h"
0035 #include "amdgpu_ucode.h"
0036 #include "amdgpu_psp.h"
0037 #include "atom.h"
0038 #include "amd_pcie.h"
0039 
0040 #include "gc/gc_10_1_0_offset.h"
0041 #include "gc/gc_10_1_0_sh_mask.h"
0042 #include "mp/mp_11_0_offset.h"
0043 
0044 #include "soc15.h"
0045 #include "soc15_common.h"
0046 #include "gmc_v10_0.h"
0047 #include "gfxhub_v2_0.h"
0048 #include "mmhub_v2_0.h"
0049 #include "nbio_v2_3.h"
0050 #include "nbio_v7_2.h"
0051 #include "hdp_v5_0.h"
0052 #include "nv.h"
0053 #include "navi10_ih.h"
0054 #include "gfx_v10_0.h"
0055 #include "sdma_v5_0.h"
0056 #include "sdma_v5_2.h"
0057 #include "vcn_v2_0.h"
0058 #include "jpeg_v2_0.h"
0059 #include "vcn_v3_0.h"
0060 #include "jpeg_v3_0.h"
0061 #include "amdgpu_vkms.h"
0062 #include "mes_v10_1.h"
0063 #include "mxgpu_nv.h"
0064 #include "smuio_v11_0.h"
0065 #include "smuio_v11_0_6.h"
0066 
0067 static const struct amd_ip_funcs nv_common_ip_funcs;
0068 
0069 /* Navi */
0070 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
0071 {
0072     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
0073     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
0074 };
0075 
0076 static const struct amdgpu_video_codecs nv_video_codecs_encode =
0077 {
0078     .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
0079     .codec_array = nv_video_codecs_encode_array,
0080 };
0081 
0082 /* Navi1x */
0083 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
0084 {
0085     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
0086     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
0087     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0088     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
0089     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
0090     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0091     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
0092 };
0093 
0094 static const struct amdgpu_video_codecs nv_video_codecs_decode =
0095 {
0096     .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
0097     .codec_array = nv_video_codecs_decode_array,
0098 };
0099 
0100 /* Sienna Cichlid */
0101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
0102 {
0103     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
0104     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
0105     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0106     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
0107     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
0108     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0109     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
0110     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
0111 };
0112 
0113 static const struct amdgpu_video_codecs sc_video_codecs_decode =
0114 {
0115     .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
0116     .codec_array = sc_video_codecs_decode_array,
0117 };
0118 
0119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
0120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
0121 {
0122     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
0123     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
0124 };
0125 
0126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
0127 {
0128     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
0129     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
0130     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0131     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
0132     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
0133     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0134     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
0135     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
0136 };
0137 
0138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
0139 {
0140     .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
0141     .codec_array = sriov_sc_video_codecs_encode_array,
0142 };
0143 
0144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
0145 {
0146     .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
0147     .codec_array = sriov_sc_video_codecs_decode_array,
0148 };
0149 
0150 /* Beige Goby*/
0151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
0152     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0153     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
0154     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
0155 };
0156 
0157 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
0158     .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
0159     .codec_array = bg_video_codecs_decode_array,
0160 };
0161 
0162 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
0163     .codec_count = 0,
0164     .codec_array = NULL,
0165 };
0166 
0167 /* Yellow Carp*/
0168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
0169     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
0170     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
0171     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
0172     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
0173     {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
0174 };
0175 
0176 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
0177     .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
0178     .codec_array = yc_video_codecs_decode_array,
0179 };
0180 
0181 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
0182                  const struct amdgpu_video_codecs **codecs)
0183 {
0184     switch (adev->ip_versions[UVD_HWIP][0]) {
0185     case IP_VERSION(3, 0, 0):
0186     case IP_VERSION(3, 0, 64):
0187     case IP_VERSION(3, 0, 192):
0188         if (amdgpu_sriov_vf(adev)) {
0189             if (encode)
0190                 *codecs = &sriov_sc_video_codecs_encode;
0191             else
0192                 *codecs = &sriov_sc_video_codecs_decode;
0193         } else {
0194             if (encode)
0195                 *codecs = &nv_video_codecs_encode;
0196             else
0197                 *codecs = &sc_video_codecs_decode;
0198         }
0199         return 0;
0200     case IP_VERSION(3, 0, 16):
0201     case IP_VERSION(3, 0, 2):
0202         if (encode)
0203             *codecs = &nv_video_codecs_encode;
0204         else
0205             *codecs = &sc_video_codecs_decode;
0206         return 0;
0207     case IP_VERSION(3, 1, 1):
0208     case IP_VERSION(3, 1, 2):
0209         if (encode)
0210             *codecs = &nv_video_codecs_encode;
0211         else
0212             *codecs = &yc_video_codecs_decode;
0213         return 0;
0214     case IP_VERSION(3, 0, 33):
0215         if (encode)
0216             *codecs = &bg_video_codecs_encode;
0217         else
0218             *codecs = &bg_video_codecs_decode;
0219         return 0;
0220     case IP_VERSION(2, 0, 0):
0221     case IP_VERSION(2, 0, 2):
0222         if (encode)
0223             *codecs = &nv_video_codecs_encode;
0224         else
0225             *codecs = &nv_video_codecs_decode;
0226         return 0;
0227     default:
0228         return -EINVAL;
0229     }
0230 }
0231 
0232 /*
0233  * Indirect registers accessor
0234  */
0235 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
0236 {
0237     unsigned long address, data;
0238     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0239     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0240 
0241     return amdgpu_device_indirect_rreg(adev, address, data, reg);
0242 }
0243 
0244 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0245 {
0246     unsigned long address, data;
0247 
0248     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0249     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0250 
0251     amdgpu_device_indirect_wreg(adev, address, data, reg, v);
0252 }
0253 
0254 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
0255 {
0256     unsigned long address, data;
0257     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0258     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0259 
0260     return amdgpu_device_indirect_rreg64(adev, address, data, reg);
0261 }
0262 
0263 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
0264 {
0265     unsigned long address, data;
0266 
0267     address = adev->nbio.funcs->get_pcie_index_offset(adev);
0268     data = adev->nbio.funcs->get_pcie_data_offset(adev);
0269 
0270     amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
0271 }
0272 
0273 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
0274 {
0275     unsigned long flags, address, data;
0276     u32 r;
0277 
0278     address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
0279     data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
0280 
0281     spin_lock_irqsave(&adev->didt_idx_lock, flags);
0282     WREG32(address, (reg));
0283     r = RREG32(data);
0284     spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
0285     return r;
0286 }
0287 
0288 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
0289 {
0290     unsigned long flags, address, data;
0291 
0292     address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
0293     data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
0294 
0295     spin_lock_irqsave(&adev->didt_idx_lock, flags);
0296     WREG32(address, (reg));
0297     WREG32(data, (v));
0298     spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
0299 }
0300 
0301 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
0302 {
0303     return adev->nbio.funcs->get_memsize(adev);
0304 }
0305 
0306 static u32 nv_get_xclk(struct amdgpu_device *adev)
0307 {
0308     return adev->clock.spll.reference_freq;
0309 }
0310 
0311 
0312 void nv_grbm_select(struct amdgpu_device *adev,
0313              u32 me, u32 pipe, u32 queue, u32 vmid)
0314 {
0315     u32 grbm_gfx_cntl = 0;
0316     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
0317     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
0318     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
0319     grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
0320 
0321     WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
0322 }
0323 
0324 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
0325 {
0326     /* todo */
0327 }
0328 
0329 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
0330 {
0331     /* todo */
0332     return false;
0333 }
0334 
0335 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
0336     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
0337     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
0338     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
0339     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
0340     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
0341     { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
0342     { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
0343     { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
0344     { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
0345     { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
0346     { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
0347     { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
0348     { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
0349     { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
0350     { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
0351     { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
0352     { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
0353     { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
0354     { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
0355 };
0356 
0357 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
0358                      u32 sh_num, u32 reg_offset)
0359 {
0360     uint32_t val;
0361 
0362     mutex_lock(&adev->grbm_idx_mutex);
0363     if (se_num != 0xffffffff || sh_num != 0xffffffff)
0364         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
0365 
0366     val = RREG32(reg_offset);
0367 
0368     if (se_num != 0xffffffff || sh_num != 0xffffffff)
0369         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
0370     mutex_unlock(&adev->grbm_idx_mutex);
0371     return val;
0372 }
0373 
0374 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
0375                       bool indexed, u32 se_num,
0376                       u32 sh_num, u32 reg_offset)
0377 {
0378     if (indexed) {
0379         return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
0380     } else {
0381         if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
0382             return adev->gfx.config.gb_addr_config;
0383         return RREG32(reg_offset);
0384     }
0385 }
0386 
0387 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
0388                 u32 sh_num, u32 reg_offset, u32 *value)
0389 {
0390     uint32_t i;
0391     struct soc15_allowed_register_entry  *en;
0392 
0393     *value = 0;
0394     for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
0395         en = &nv_allowed_read_registers[i];
0396         if (adev->reg_offset[en->hwip][en->inst] &&
0397             reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
0398                    + en->reg_offset))
0399             continue;
0400 
0401         *value = nv_get_register_value(adev,
0402                            nv_allowed_read_registers[i].grbm_indexed,
0403                            se_num, sh_num, reg_offset);
0404         return 0;
0405     }
0406     return -EINVAL;
0407 }
0408 
0409 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
0410 {
0411     u32 i;
0412     int ret = 0;
0413 
0414     amdgpu_atombios_scratch_regs_engine_hung(adev, true);
0415 
0416     /* disable BM */
0417     pci_clear_master(adev->pdev);
0418 
0419     amdgpu_device_cache_pci_state(adev->pdev);
0420 
0421     ret = amdgpu_dpm_mode2_reset(adev);
0422     if (ret)
0423         dev_err(adev->dev, "GPU mode2 reset failed\n");
0424 
0425     amdgpu_device_load_pci_state(adev->pdev);
0426 
0427     /* wait for asic to come out of reset */
0428     for (i = 0; i < adev->usec_timeout; i++) {
0429         u32 memsize = adev->nbio.funcs->get_memsize(adev);
0430 
0431         if (memsize != 0xffffffff)
0432             break;
0433         udelay(1);
0434     }
0435 
0436     amdgpu_atombios_scratch_regs_engine_hung(adev, false);
0437 
0438     return ret;
0439 }
0440 
0441 static enum amd_reset_method
0442 nv_asic_reset_method(struct amdgpu_device *adev)
0443 {
0444     if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
0445         amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
0446         amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
0447         amdgpu_reset_method == AMD_RESET_METHOD_PCI)
0448         return amdgpu_reset_method;
0449 
0450     if (amdgpu_reset_method != -1)
0451         dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
0452                   amdgpu_reset_method);
0453 
0454     switch (adev->ip_versions[MP1_HWIP][0]) {
0455     case IP_VERSION(11, 5, 0):
0456     case IP_VERSION(13, 0, 1):
0457     case IP_VERSION(13, 0, 3):
0458     case IP_VERSION(13, 0, 5):
0459     case IP_VERSION(13, 0, 8):
0460         return AMD_RESET_METHOD_MODE2;
0461     case IP_VERSION(11, 0, 7):
0462     case IP_VERSION(11, 0, 11):
0463     case IP_VERSION(11, 0, 12):
0464     case IP_VERSION(11, 0, 13):
0465         return AMD_RESET_METHOD_MODE1;
0466     default:
0467         if (amdgpu_dpm_is_baco_supported(adev))
0468             return AMD_RESET_METHOD_BACO;
0469         else
0470             return AMD_RESET_METHOD_MODE1;
0471     }
0472 }
0473 
0474 static int nv_asic_reset(struct amdgpu_device *adev)
0475 {
0476     int ret = 0;
0477 
0478     switch (nv_asic_reset_method(adev)) {
0479     case AMD_RESET_METHOD_PCI:
0480         dev_info(adev->dev, "PCI reset\n");
0481         ret = amdgpu_device_pci_reset(adev);
0482         break;
0483     case AMD_RESET_METHOD_BACO:
0484         dev_info(adev->dev, "BACO reset\n");
0485         ret = amdgpu_dpm_baco_reset(adev);
0486         break;
0487     case AMD_RESET_METHOD_MODE2:
0488         dev_info(adev->dev, "MODE2 reset\n");
0489         ret = nv_asic_mode2_reset(adev);
0490         break;
0491     default:
0492         dev_info(adev->dev, "MODE1 reset\n");
0493         ret = amdgpu_device_mode1_reset(adev);
0494         break;
0495     }
0496 
0497     return ret;
0498 }
0499 
0500 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
0501 {
0502     /* todo */
0503     return 0;
0504 }
0505 
0506 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
0507 {
0508     /* todo */
0509     return 0;
0510 }
0511 
0512 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
0513 {
0514     if (pci_is_root_bus(adev->pdev->bus))
0515         return;
0516 
0517     if (amdgpu_pcie_gen2 == 0)
0518         return;
0519 
0520     if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
0521                     CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
0522         return;
0523 
0524     /* todo */
0525 }
0526 
0527 static void nv_program_aspm(struct amdgpu_device *adev)
0528 {
0529     if (!amdgpu_device_should_use_aspm(adev))
0530         return;
0531 
0532     if (!(adev->flags & AMD_IS_APU) &&
0533         (adev->nbio.funcs->program_aspm))
0534         adev->nbio.funcs->program_aspm(adev);
0535 
0536 }
0537 
0538 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
0539                     bool enable)
0540 {
0541     adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
0542     adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
0543 }
0544 
0545 const struct amdgpu_ip_block_version nv_common_ip_block =
0546 {
0547     .type = AMD_IP_BLOCK_TYPE_COMMON,
0548     .major = 1,
0549     .minor = 0,
0550     .rev = 0,
0551     .funcs = &nv_common_ip_funcs,
0552 };
0553 
0554 void nv_set_virt_ops(struct amdgpu_device *adev)
0555 {
0556     adev->virt.ops = &xgpu_nv_virt_ops;
0557 }
0558 
0559 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
0560 {
0561     return adev->nbio.funcs->get_rev_id(adev);
0562 }
0563 
0564 static bool nv_need_full_reset(struct amdgpu_device *adev)
0565 {
0566     return true;
0567 }
0568 
0569 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
0570 {
0571     u32 sol_reg;
0572 
0573     if (adev->flags & AMD_IS_APU)
0574         return false;
0575 
0576     /* Check sOS sign of life register to confirm sys driver and sOS
0577      * are already been loaded.
0578      */
0579     sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
0580     if (sol_reg)
0581         return true;
0582 
0583     return false;
0584 }
0585 
0586 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
0587 {
0588 
0589     /* TODO
0590      * dummy implement for pcie_replay_count sysfs interface
0591      * */
0592 
0593     return 0;
0594 }
0595 
0596 static void nv_init_doorbell_index(struct amdgpu_device *adev)
0597 {
0598     adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
0599     adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
0600     adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
0601     adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
0602     adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
0603     adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
0604     adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
0605     adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
0606     adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
0607     adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
0608     adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
0609     adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
0610     adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
0611     adev->doorbell_index.gfx_userqueue_start =
0612         AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
0613     adev->doorbell_index.gfx_userqueue_end =
0614         AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
0615     adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
0616     adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
0617     adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
0618     adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
0619     adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
0620     adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
0621     adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
0622     adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
0623     adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
0624     adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
0625     adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
0626     adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
0627     adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
0628 
0629     adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
0630     adev->doorbell_index.sdma_doorbell_range = 20;
0631 }
0632 
0633 static void nv_pre_asic_init(struct amdgpu_device *adev)
0634 {
0635 }
0636 
0637 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
0638                        bool enter)
0639 {
0640     if (enter)
0641         amdgpu_gfx_rlc_enter_safe_mode(adev);
0642     else
0643         amdgpu_gfx_rlc_exit_safe_mode(adev);
0644 
0645     if (adev->gfx.funcs->update_perfmon_mgcg)
0646         adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
0647 
0648     if (!(adev->flags & AMD_IS_APU) &&
0649         (adev->nbio.funcs->enable_aspm) &&
0650          amdgpu_device_should_use_aspm(adev))
0651         adev->nbio.funcs->enable_aspm(adev, !enter);
0652 
0653     return 0;
0654 }
0655 
0656 static const struct amdgpu_asic_funcs nv_asic_funcs =
0657 {
0658     .read_disabled_bios = &nv_read_disabled_bios,
0659     .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
0660     .read_register = &nv_read_register,
0661     .reset = &nv_asic_reset,
0662     .reset_method = &nv_asic_reset_method,
0663     .set_vga_state = &nv_vga_set_state,
0664     .get_xclk = &nv_get_xclk,
0665     .set_uvd_clocks = &nv_set_uvd_clocks,
0666     .set_vce_clocks = &nv_set_vce_clocks,
0667     .get_config_memsize = &nv_get_config_memsize,
0668     .init_doorbell_index = &nv_init_doorbell_index,
0669     .need_full_reset = &nv_need_full_reset,
0670     .need_reset_on_init = &nv_need_reset_on_init,
0671     .get_pcie_replay_count = &nv_get_pcie_replay_count,
0672     .supports_baco = &amdgpu_dpm_is_baco_supported,
0673     .pre_asic_init = &nv_pre_asic_init,
0674     .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
0675     .query_video_codecs = &nv_query_video_codecs,
0676 };
0677 
0678 static int nv_common_early_init(void *handle)
0679 {
0680 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
0681     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0682 
0683     if (!amdgpu_sriov_vf(adev)) {
0684         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
0685         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
0686     }
0687     adev->smc_rreg = NULL;
0688     adev->smc_wreg = NULL;
0689     adev->pcie_rreg = &nv_pcie_rreg;
0690     adev->pcie_wreg = &nv_pcie_wreg;
0691     adev->pcie_rreg64 = &nv_pcie_rreg64;
0692     adev->pcie_wreg64 = &nv_pcie_wreg64;
0693     adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
0694     adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
0695 
0696     /* TODO: will add them during VCN v2 implementation */
0697     adev->uvd_ctx_rreg = NULL;
0698     adev->uvd_ctx_wreg = NULL;
0699 
0700     adev->didt_rreg = &nv_didt_rreg;
0701     adev->didt_wreg = &nv_didt_wreg;
0702 
0703     adev->asic_funcs = &nv_asic_funcs;
0704 
0705     adev->rev_id = nv_get_rev_id(adev);
0706     adev->external_rev_id = 0xff;
0707     /* TODO: split the GC and PG flags based on the relevant IP version for which
0708      * they are relevant.
0709      */
0710     switch (adev->ip_versions[GC_HWIP][0]) {
0711     case IP_VERSION(10, 1, 10):
0712         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0713             AMD_CG_SUPPORT_GFX_CGCG |
0714             AMD_CG_SUPPORT_IH_CG |
0715             AMD_CG_SUPPORT_HDP_MGCG |
0716             AMD_CG_SUPPORT_HDP_LS |
0717             AMD_CG_SUPPORT_SDMA_MGCG |
0718             AMD_CG_SUPPORT_SDMA_LS |
0719             AMD_CG_SUPPORT_MC_MGCG |
0720             AMD_CG_SUPPORT_MC_LS |
0721             AMD_CG_SUPPORT_ATHUB_MGCG |
0722             AMD_CG_SUPPORT_ATHUB_LS |
0723             AMD_CG_SUPPORT_VCN_MGCG |
0724             AMD_CG_SUPPORT_JPEG_MGCG |
0725             AMD_CG_SUPPORT_BIF_MGCG |
0726             AMD_CG_SUPPORT_BIF_LS;
0727         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0728             AMD_PG_SUPPORT_VCN_DPG |
0729             AMD_PG_SUPPORT_JPEG |
0730             AMD_PG_SUPPORT_ATHUB;
0731         adev->external_rev_id = adev->rev_id + 0x1;
0732         break;
0733     case IP_VERSION(10, 1, 1):
0734         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0735             AMD_CG_SUPPORT_GFX_CGCG |
0736             AMD_CG_SUPPORT_IH_CG |
0737             AMD_CG_SUPPORT_HDP_MGCG |
0738             AMD_CG_SUPPORT_HDP_LS |
0739             AMD_CG_SUPPORT_SDMA_MGCG |
0740             AMD_CG_SUPPORT_SDMA_LS |
0741             AMD_CG_SUPPORT_MC_MGCG |
0742             AMD_CG_SUPPORT_MC_LS |
0743             AMD_CG_SUPPORT_ATHUB_MGCG |
0744             AMD_CG_SUPPORT_ATHUB_LS |
0745             AMD_CG_SUPPORT_VCN_MGCG |
0746             AMD_CG_SUPPORT_JPEG_MGCG |
0747             AMD_CG_SUPPORT_BIF_MGCG |
0748             AMD_CG_SUPPORT_BIF_LS;
0749         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0750             AMD_PG_SUPPORT_JPEG |
0751             AMD_PG_SUPPORT_VCN_DPG;
0752         adev->external_rev_id = adev->rev_id + 20;
0753         break;
0754     case IP_VERSION(10, 1, 2):
0755         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0756             AMD_CG_SUPPORT_GFX_MGLS |
0757             AMD_CG_SUPPORT_GFX_CGCG |
0758             AMD_CG_SUPPORT_GFX_CP_LS |
0759             AMD_CG_SUPPORT_GFX_RLC_LS |
0760             AMD_CG_SUPPORT_IH_CG |
0761             AMD_CG_SUPPORT_HDP_MGCG |
0762             AMD_CG_SUPPORT_HDP_LS |
0763             AMD_CG_SUPPORT_SDMA_MGCG |
0764             AMD_CG_SUPPORT_SDMA_LS |
0765             AMD_CG_SUPPORT_MC_MGCG |
0766             AMD_CG_SUPPORT_MC_LS |
0767             AMD_CG_SUPPORT_ATHUB_MGCG |
0768             AMD_CG_SUPPORT_ATHUB_LS |
0769             AMD_CG_SUPPORT_VCN_MGCG |
0770             AMD_CG_SUPPORT_JPEG_MGCG;
0771         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0772             AMD_PG_SUPPORT_VCN_DPG |
0773             AMD_PG_SUPPORT_JPEG |
0774             AMD_PG_SUPPORT_ATHUB;
0775         /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
0776          * as a consequence, the rev_id and external_rev_id are wrong.
0777          * workaround it by hardcoding rev_id to 0 (default value).
0778          */
0779         if (amdgpu_sriov_vf(adev))
0780             adev->rev_id = 0;
0781         adev->external_rev_id = adev->rev_id + 0xa;
0782         break;
0783     case IP_VERSION(10, 3, 0):
0784         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0785             AMD_CG_SUPPORT_GFX_CGCG |
0786             AMD_CG_SUPPORT_GFX_CGLS |
0787             AMD_CG_SUPPORT_GFX_3D_CGCG |
0788             AMD_CG_SUPPORT_MC_MGCG |
0789             AMD_CG_SUPPORT_VCN_MGCG |
0790             AMD_CG_SUPPORT_JPEG_MGCG |
0791             AMD_CG_SUPPORT_HDP_MGCG |
0792             AMD_CG_SUPPORT_HDP_LS |
0793             AMD_CG_SUPPORT_IH_CG |
0794             AMD_CG_SUPPORT_MC_LS;
0795         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0796             AMD_PG_SUPPORT_VCN_DPG |
0797             AMD_PG_SUPPORT_JPEG |
0798             AMD_PG_SUPPORT_ATHUB |
0799             AMD_PG_SUPPORT_MMHUB;
0800         if (amdgpu_sriov_vf(adev)) {
0801             /* hypervisor control CG and PG enablement */
0802             adev->cg_flags = 0;
0803             adev->pg_flags = 0;
0804         }
0805         adev->external_rev_id = adev->rev_id + 0x28;
0806         break;
0807     case IP_VERSION(10, 3, 2):
0808         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0809             AMD_CG_SUPPORT_GFX_CGCG |
0810             AMD_CG_SUPPORT_GFX_CGLS |
0811             AMD_CG_SUPPORT_GFX_3D_CGCG |
0812             AMD_CG_SUPPORT_VCN_MGCG |
0813             AMD_CG_SUPPORT_JPEG_MGCG |
0814             AMD_CG_SUPPORT_MC_MGCG |
0815             AMD_CG_SUPPORT_MC_LS |
0816             AMD_CG_SUPPORT_HDP_MGCG |
0817             AMD_CG_SUPPORT_HDP_LS |
0818             AMD_CG_SUPPORT_IH_CG;
0819         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0820             AMD_PG_SUPPORT_VCN_DPG |
0821             AMD_PG_SUPPORT_JPEG |
0822             AMD_PG_SUPPORT_ATHUB |
0823             AMD_PG_SUPPORT_MMHUB;
0824         adev->external_rev_id = adev->rev_id + 0x32;
0825         break;
0826     case IP_VERSION(10, 3, 1):
0827         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0828             AMD_CG_SUPPORT_GFX_MGLS |
0829             AMD_CG_SUPPORT_GFX_CP_LS |
0830             AMD_CG_SUPPORT_GFX_RLC_LS |
0831             AMD_CG_SUPPORT_GFX_CGCG |
0832             AMD_CG_SUPPORT_GFX_CGLS |
0833             AMD_CG_SUPPORT_GFX_3D_CGCG |
0834             AMD_CG_SUPPORT_GFX_3D_CGLS |
0835             AMD_CG_SUPPORT_MC_MGCG |
0836             AMD_CG_SUPPORT_MC_LS |
0837             AMD_CG_SUPPORT_GFX_FGCG |
0838             AMD_CG_SUPPORT_VCN_MGCG |
0839             AMD_CG_SUPPORT_SDMA_MGCG |
0840             AMD_CG_SUPPORT_SDMA_LS |
0841             AMD_CG_SUPPORT_JPEG_MGCG;
0842         adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
0843             AMD_PG_SUPPORT_VCN |
0844             AMD_PG_SUPPORT_VCN_DPG |
0845             AMD_PG_SUPPORT_JPEG;
0846         if (adev->apu_flags & AMD_APU_IS_VANGOGH)
0847             adev->external_rev_id = adev->rev_id + 0x01;
0848         break;
0849     case IP_VERSION(10, 3, 4):
0850         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0851             AMD_CG_SUPPORT_GFX_CGCG |
0852             AMD_CG_SUPPORT_GFX_CGLS |
0853             AMD_CG_SUPPORT_GFX_3D_CGCG |
0854             AMD_CG_SUPPORT_VCN_MGCG |
0855             AMD_CG_SUPPORT_JPEG_MGCG |
0856             AMD_CG_SUPPORT_MC_MGCG |
0857             AMD_CG_SUPPORT_MC_LS |
0858             AMD_CG_SUPPORT_HDP_MGCG |
0859             AMD_CG_SUPPORT_HDP_LS |
0860             AMD_CG_SUPPORT_IH_CG;
0861         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0862             AMD_PG_SUPPORT_VCN_DPG |
0863             AMD_PG_SUPPORT_JPEG |
0864             AMD_PG_SUPPORT_ATHUB |
0865             AMD_PG_SUPPORT_MMHUB;
0866         adev->external_rev_id = adev->rev_id + 0x3c;
0867         break;
0868     case IP_VERSION(10, 3, 5):
0869         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0870             AMD_CG_SUPPORT_GFX_CGCG |
0871             AMD_CG_SUPPORT_GFX_CGLS |
0872             AMD_CG_SUPPORT_GFX_3D_CGCG |
0873             AMD_CG_SUPPORT_MC_MGCG |
0874             AMD_CG_SUPPORT_MC_LS |
0875             AMD_CG_SUPPORT_HDP_MGCG |
0876             AMD_CG_SUPPORT_HDP_LS |
0877             AMD_CG_SUPPORT_IH_CG |
0878             AMD_CG_SUPPORT_VCN_MGCG;
0879         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0880             AMD_PG_SUPPORT_VCN_DPG |
0881             AMD_PG_SUPPORT_ATHUB |
0882             AMD_PG_SUPPORT_MMHUB;
0883         adev->external_rev_id = adev->rev_id + 0x46;
0884         break;
0885     case IP_VERSION(10, 3, 3):
0886         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0887             AMD_CG_SUPPORT_GFX_MGLS |
0888             AMD_CG_SUPPORT_GFX_CGCG |
0889             AMD_CG_SUPPORT_GFX_CGLS |
0890             AMD_CG_SUPPORT_GFX_3D_CGCG |
0891             AMD_CG_SUPPORT_GFX_3D_CGLS |
0892             AMD_CG_SUPPORT_GFX_RLC_LS |
0893             AMD_CG_SUPPORT_GFX_CP_LS |
0894             AMD_CG_SUPPORT_GFX_FGCG |
0895             AMD_CG_SUPPORT_MC_MGCG |
0896             AMD_CG_SUPPORT_MC_LS |
0897             AMD_CG_SUPPORT_SDMA_LS |
0898             AMD_CG_SUPPORT_HDP_MGCG |
0899             AMD_CG_SUPPORT_HDP_LS |
0900             AMD_CG_SUPPORT_ATHUB_MGCG |
0901             AMD_CG_SUPPORT_ATHUB_LS |
0902             AMD_CG_SUPPORT_IH_CG |
0903             AMD_CG_SUPPORT_VCN_MGCG |
0904             AMD_CG_SUPPORT_JPEG_MGCG;
0905         adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
0906             AMD_PG_SUPPORT_VCN |
0907             AMD_PG_SUPPORT_VCN_DPG |
0908             AMD_PG_SUPPORT_JPEG;
0909         if (adev->pdev->device == 0x1681)
0910             adev->external_rev_id = 0x20;
0911         else
0912             adev->external_rev_id = adev->rev_id + 0x01;
0913         break;
0914     case IP_VERSION(10, 1, 3):
0915     case IP_VERSION(10, 1, 4):
0916         adev->cg_flags = 0;
0917         adev->pg_flags = 0;
0918         adev->external_rev_id = adev->rev_id + 0x82;
0919         break;
0920     case IP_VERSION(10, 3, 6):
0921         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
0922             AMD_CG_SUPPORT_GFX_MGLS |
0923             AMD_CG_SUPPORT_GFX_CGCG |
0924             AMD_CG_SUPPORT_GFX_CGLS |
0925             AMD_CG_SUPPORT_GFX_3D_CGCG |
0926             AMD_CG_SUPPORT_GFX_3D_CGLS |
0927             AMD_CG_SUPPORT_GFX_RLC_LS |
0928             AMD_CG_SUPPORT_GFX_CP_LS |
0929             AMD_CG_SUPPORT_GFX_FGCG |
0930             AMD_CG_SUPPORT_MC_MGCG |
0931             AMD_CG_SUPPORT_MC_LS |
0932             AMD_CG_SUPPORT_SDMA_LS |
0933             AMD_CG_SUPPORT_HDP_MGCG |
0934             AMD_CG_SUPPORT_HDP_LS |
0935             AMD_CG_SUPPORT_ATHUB_MGCG |
0936             AMD_CG_SUPPORT_ATHUB_LS |
0937             AMD_CG_SUPPORT_IH_CG |
0938             AMD_CG_SUPPORT_VCN_MGCG |
0939             AMD_CG_SUPPORT_JPEG_MGCG;
0940         adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
0941             AMD_PG_SUPPORT_VCN |
0942             AMD_PG_SUPPORT_VCN_DPG |
0943             AMD_PG_SUPPORT_JPEG;
0944         adev->external_rev_id = adev->rev_id + 0x01;
0945         break;
0946     case IP_VERSION(10, 3, 7):
0947         adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
0948             AMD_CG_SUPPORT_GFX_MGLS |
0949             AMD_CG_SUPPORT_GFX_CGCG |
0950             AMD_CG_SUPPORT_GFX_CGLS |
0951             AMD_CG_SUPPORT_GFX_3D_CGCG |
0952             AMD_CG_SUPPORT_GFX_3D_CGLS |
0953             AMD_CG_SUPPORT_GFX_RLC_LS |
0954             AMD_CG_SUPPORT_GFX_CP_LS |
0955             AMD_CG_SUPPORT_GFX_FGCG |
0956             AMD_CG_SUPPORT_MC_MGCG |
0957             AMD_CG_SUPPORT_MC_LS |
0958             AMD_CG_SUPPORT_SDMA_LS |
0959             AMD_CG_SUPPORT_HDP_MGCG |
0960             AMD_CG_SUPPORT_HDP_LS |
0961             AMD_CG_SUPPORT_ATHUB_MGCG |
0962             AMD_CG_SUPPORT_ATHUB_LS |
0963             AMD_CG_SUPPORT_IH_CG |
0964             AMD_CG_SUPPORT_VCN_MGCG |
0965             AMD_CG_SUPPORT_JPEG_MGCG;
0966         adev->pg_flags = AMD_PG_SUPPORT_VCN |
0967             AMD_PG_SUPPORT_VCN_DPG |
0968             AMD_PG_SUPPORT_JPEG |
0969             AMD_PG_SUPPORT_GFX_PG;
0970         adev->external_rev_id = adev->rev_id + 0x01;
0971         break;
0972     default:
0973         /* FIXME: not supported yet */
0974         return -EINVAL;
0975     }
0976 
0977     if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
0978         adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
0979                     AMD_PG_SUPPORT_VCN_DPG |
0980                     AMD_PG_SUPPORT_JPEG);
0981 
0982     if (amdgpu_sriov_vf(adev)) {
0983         amdgpu_virt_init_setting(adev);
0984         xgpu_nv_mailbox_set_irq_funcs(adev);
0985     }
0986 
0987     return 0;
0988 }
0989 
0990 static int nv_common_late_init(void *handle)
0991 {
0992     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0993 
0994     if (amdgpu_sriov_vf(adev)) {
0995         xgpu_nv_mailbox_get_irq(adev);
0996         amdgpu_virt_update_sriov_video_codec(adev,
0997                 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
0998                 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
0999     }
1000 
1001     return 0;
1002 }
1003 
1004 static int nv_common_sw_init(void *handle)
1005 {
1006     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007 
1008     if (amdgpu_sriov_vf(adev))
1009         xgpu_nv_mailbox_add_irq_id(adev);
1010 
1011     return 0;
1012 }
1013 
1014 static int nv_common_sw_fini(void *handle)
1015 {
1016     return 0;
1017 }
1018 
1019 static int nv_common_hw_init(void *handle)
1020 {
1021     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022 
1023     if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1024         adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1025 
1026     if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1027         adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1028 
1029     /* enable pcie gen2/3 link */
1030     nv_pcie_gen3_enable(adev);
1031     /* enable aspm */
1032     nv_program_aspm(adev);
1033     /* setup nbio registers */
1034     adev->nbio.funcs->init_registers(adev);
1035     /* remap HDP registers to a hole in mmio space,
1036      * for the purpose of expose those registers
1037      * to process space
1038      */
1039     if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1040         adev->nbio.funcs->remap_hdp_registers(adev);
1041     /* enable the doorbell aperture */
1042     nv_enable_doorbell_aperture(adev, true);
1043 
1044     return 0;
1045 }
1046 
1047 static int nv_common_hw_fini(void *handle)
1048 {
1049     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050 
1051     /* disable the doorbell aperture */
1052     nv_enable_doorbell_aperture(adev, false);
1053 
1054     return 0;
1055 }
1056 
1057 static int nv_common_suspend(void *handle)
1058 {
1059     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1060 
1061     return nv_common_hw_fini(adev);
1062 }
1063 
1064 static int nv_common_resume(void *handle)
1065 {
1066     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067 
1068     return nv_common_hw_init(adev);
1069 }
1070 
1071 static bool nv_common_is_idle(void *handle)
1072 {
1073     return true;
1074 }
1075 
1076 static int nv_common_wait_for_idle(void *handle)
1077 {
1078     return 0;
1079 }
1080 
1081 static int nv_common_soft_reset(void *handle)
1082 {
1083     return 0;
1084 }
1085 
1086 static int nv_common_set_clockgating_state(void *handle,
1087                        enum amd_clockgating_state state)
1088 {
1089     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090 
1091     if (amdgpu_sriov_vf(adev))
1092         return 0;
1093 
1094     switch (adev->ip_versions[NBIO_HWIP][0]) {
1095     case IP_VERSION(2, 3, 0):
1096     case IP_VERSION(2, 3, 1):
1097     case IP_VERSION(2, 3, 2):
1098     case IP_VERSION(3, 3, 0):
1099     case IP_VERSION(3, 3, 1):
1100     case IP_VERSION(3, 3, 2):
1101     case IP_VERSION(3, 3, 3):
1102         adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1103                 state == AMD_CG_STATE_GATE);
1104         adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1105                 state == AMD_CG_STATE_GATE);
1106         adev->hdp.funcs->update_clock_gating(adev,
1107                 state == AMD_CG_STATE_GATE);
1108         adev->smuio.funcs->update_rom_clock_gating(adev,
1109                 state == AMD_CG_STATE_GATE);
1110         break;
1111     default:
1112         break;
1113     }
1114     return 0;
1115 }
1116 
1117 static int nv_common_set_powergating_state(void *handle,
1118                        enum amd_powergating_state state)
1119 {
1120     /* TODO */
1121     return 0;
1122 }
1123 
1124 static void nv_common_get_clockgating_state(void *handle, u64 *flags)
1125 {
1126     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1127 
1128     if (amdgpu_sriov_vf(adev))
1129         *flags = 0;
1130 
1131     adev->nbio.funcs->get_clockgating_state(adev, flags);
1132 
1133     adev->hdp.funcs->get_clock_gating_state(adev, flags);
1134 
1135     adev->smuio.funcs->get_clock_gating_state(adev, flags);
1136 
1137     return;
1138 }
1139 
1140 static const struct amd_ip_funcs nv_common_ip_funcs = {
1141     .name = "nv_common",
1142     .early_init = nv_common_early_init,
1143     .late_init = nv_common_late_init,
1144     .sw_init = nv_common_sw_init,
1145     .sw_fini = nv_common_sw_fini,
1146     .hw_init = nv_common_hw_init,
1147     .hw_fini = nv_common_hw_fini,
1148     .suspend = nv_common_suspend,
1149     .resume = nv_common_resume,
1150     .is_idle = nv_common_is_idle,
1151     .wait_for_idle = nv_common_wait_for_idle,
1152     .soft_reset = nv_common_soft_reset,
1153     .set_clockgating_state = nv_common_set_clockgating_state,
1154     .set_powergating_state = nv_common_set_powergating_state,
1155     .get_clockgating_state = nv_common_get_clockgating_state,
1156 };
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