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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "amdgpu_atombios.h"
0025 #include "nbio_v7_2.h"
0026 
0027 #include "nbio/nbio_7_2_0_offset.h"
0028 #include "nbio/nbio_7_2_0_sh_mask.h"
0029 #include <uapi/linux/kfd_ioctl.h>
0030 
0031 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC               0x0015
0032 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX      2
0033 #define regBIF_BX0_BIF_FB_EN_YC                             0x0100
0034 #define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX                    2
0035 #define regBIF1_PCIE_MST_CTRL_3                             0x4601c6
0036 #define regBIF1_PCIE_MST_CTRL_3_BASE_IDX                    5
0037 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \
0038             0x1b
0039 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \
0040             0x1c
0041 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \
0042             0x08000000L
0043 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \
0044             0x30000000L
0045 #define regBIF1_PCIE_TX_POWER_CTRL_1                        0x460187
0046 #define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX               5
0047 #define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK       0x00000001L
0048 #define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK    0x00000008L
0049 
0050 static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
0051 {
0052     WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
0053         adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
0054     WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
0055         adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
0056 }
0057 
0058 static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
0059 {
0060     u32 tmp;
0061 
0062     switch (adev->ip_versions[NBIO_HWIP][0]) {
0063     case IP_VERSION(7, 2, 1):
0064     case IP_VERSION(7, 3, 0):
0065     case IP_VERSION(7, 5, 0):
0066         tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
0067         break;
0068     default:
0069         tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
0070         break;
0071     }
0072 
0073     tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
0074     tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
0075 
0076     return tmp;
0077 }
0078 
0079 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
0080 {
0081     switch (adev->ip_versions[NBIO_HWIP][0]) {
0082     case IP_VERSION(7, 2, 1):
0083     case IP_VERSION(7, 3, 0):
0084     case IP_VERSION(7, 5, 0):
0085         if (enable)
0086             WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
0087                 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
0088                 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
0089         else
0090             WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
0091     break;
0092     default:
0093         if (enable)
0094             WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
0095                 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
0096                 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
0097         else
0098             WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
0099         break;
0100     }
0101 }
0102 
0103 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
0104 {
0105     return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
0106 }
0107 
0108 static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
0109                       bool use_doorbell, int doorbell_index,
0110                       int doorbell_size)
0111 {
0112     u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
0113     u32 doorbell_range = RREG32_PCIE_PORT(reg);
0114 
0115     if (use_doorbell) {
0116         doorbell_range = REG_SET_FIELD(doorbell_range,
0117                            GDC0_BIF_SDMA0_DOORBELL_RANGE,
0118                            OFFSET, doorbell_index);
0119         doorbell_range = REG_SET_FIELD(doorbell_range,
0120                            GDC0_BIF_SDMA0_DOORBELL_RANGE,
0121                            SIZE, doorbell_size);
0122     } else {
0123         doorbell_range = REG_SET_FIELD(doorbell_range,
0124                            GDC0_BIF_SDMA0_DOORBELL_RANGE,
0125                            SIZE, 0);
0126     }
0127 
0128     WREG32_PCIE_PORT(reg, doorbell_range);
0129 }
0130 
0131 static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
0132                      int doorbell_index, int instance)
0133 {
0134     u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
0135     u32 doorbell_range = RREG32_PCIE_PORT(reg);
0136 
0137     if (use_doorbell) {
0138         doorbell_range = REG_SET_FIELD(doorbell_range,
0139                             GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
0140                             doorbell_index);
0141         doorbell_range = REG_SET_FIELD(doorbell_range,
0142                             GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
0143     } else {
0144         doorbell_range = REG_SET_FIELD(doorbell_range,
0145                             GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
0146     }
0147 
0148     WREG32_PCIE_PORT(reg, doorbell_range);
0149 }
0150 
0151 static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
0152                            bool enable)
0153 {
0154     u32 reg;
0155 
0156     reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
0157     reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
0158                 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
0159 
0160     WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
0161 }
0162 
0163 static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
0164                             bool enable)
0165 {
0166     u32 tmp = 0;
0167 
0168     if (enable) {
0169         tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
0170                 DOORBELL_SELFRING_GPA_APER_EN, 1) |
0171             REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
0172                 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
0173             REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
0174                 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
0175 
0176         WREG32_SOC15(NBIO, 0,
0177             regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
0178             lower_32_bits(adev->doorbell.base));
0179         WREG32_SOC15(NBIO, 0,
0180             regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
0181             upper_32_bits(adev->doorbell.base));
0182     }
0183 
0184     WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
0185         tmp);
0186 }
0187 
0188 
0189 static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
0190                     bool use_doorbell, int doorbell_index)
0191 {
0192     u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
0193 
0194     if (use_doorbell) {
0195         ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
0196                           GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
0197                           doorbell_index);
0198         ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
0199                           GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
0200                           2);
0201     } else {
0202         ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
0203                           GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
0204                           0);
0205     }
0206 
0207     WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
0208              ih_doorbell_range);
0209 }
0210 
0211 static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
0212 {
0213     u32 interrupt_cntl;
0214 
0215     /* setup interrupt control */
0216     WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
0217              adev->dummy_page_addr >> 8);
0218 
0219     interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
0220     /*
0221      * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
0222      * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
0223      */
0224     interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
0225                        IH_DUMMY_RD_OVERRIDE, 0);
0226 
0227     /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
0228     interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
0229                        IH_REQ_NONSNOOP_EN, 0);
0230 
0231     WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
0232 }
0233 
0234 static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0235                                bool enable)
0236 {
0237     uint32_t def, data;
0238 
0239     def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
0240     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
0241         data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
0242              CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
0243              CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
0244              CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
0245              CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
0246              CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
0247     } else {
0248         data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
0249               CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
0250               CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
0251               CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
0252               CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
0253               CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
0254     }
0255 
0256     if (def != data)
0257         WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
0258 }
0259 
0260 static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0261                               bool enable)
0262 {
0263     uint32_t def, data;
0264 
0265     switch (adev->ip_versions[NBIO_HWIP][0]) {
0266     case IP_VERSION(7, 2, 1):
0267     case IP_VERSION(7, 3, 0):
0268     case IP_VERSION(7, 5, 0):
0269         def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
0270         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
0271             data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
0272         else
0273             data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
0274 
0275         if (def != data)
0276             WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
0277 
0278         def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0,
0279             regBIF1_PCIE_TX_POWER_CTRL_1));
0280         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
0281             data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
0282                 BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
0283         else
0284             data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
0285                 BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
0286 
0287         if (def != data)
0288             WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
0289                 data);
0290         break;
0291     default:
0292         def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
0293         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
0294             data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
0295                  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
0296                  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
0297         else
0298             data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
0299                   PCIE_CNTL2__MST_MEM_LS_EN_MASK |
0300                   PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
0301 
0302         if (def != data)
0303             WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
0304         break;
0305     }
0306 }
0307 
0308 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
0309                         u64 *flags)
0310 {
0311     int data;
0312 
0313     /* AMD_CG_SUPPORT_BIF_MGCG */
0314     data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
0315     if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
0316         *flags |= AMD_CG_SUPPORT_BIF_MGCG;
0317 
0318     /* AMD_CG_SUPPORT_BIF_LS */
0319     data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
0320     if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
0321         *flags |= AMD_CG_SUPPORT_BIF_LS;
0322 }
0323 
0324 static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
0325 {
0326     return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
0327 }
0328 
0329 static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
0330 {
0331     return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
0332 }
0333 
0334 static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
0335 {
0336     return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
0337 }
0338 
0339 static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
0340 {
0341     return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
0342 }
0343 
0344 static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
0345 {
0346     return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
0347 }
0348 
0349 static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
0350 {
0351     return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
0352 }
0353 
0354 const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
0355     .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
0356     .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
0357     .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
0358     .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
0359     .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
0360     .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
0361     .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
0362     .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
0363     .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
0364     .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
0365     .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
0366     .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
0367 };
0368 
0369 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
0370 {
0371     uint32_t def, data;
0372     switch (adev->ip_versions[NBIO_HWIP][0]) {
0373     case IP_VERSION(7, 2, 1):
0374     case IP_VERSION(7, 3, 0):
0375     case IP_VERSION(7, 5, 0):
0376         def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
0377         data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
0378             CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
0379         data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
0380             CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
0381 
0382         if (def != data)
0383             WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
0384         break;
0385     default:
0386         def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
0387         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
0388             CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
0389         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
0390             CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
0391 
0392         if (def != data)
0393             WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
0394         break;
0395     }
0396 
0397     if (amdgpu_sriov_vf(adev))
0398         adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
0399             regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
0400 }
0401 
0402 const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
0403     .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
0404     .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
0405     .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
0406     .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
0407     .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
0408     .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
0409     .get_rev_id = nbio_v7_2_get_rev_id,
0410     .mc_access_enable = nbio_v7_2_mc_access_enable,
0411     .get_memsize = nbio_v7_2_get_memsize,
0412     .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
0413     .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
0414     .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
0415     .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
0416     .ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
0417     .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
0418     .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
0419     .get_clockgating_state = nbio_v7_2_get_clockgating_state,
0420     .ih_control = nbio_v7_2_ih_control,
0421     .init_registers = nbio_v7_2_init_registers,
0422     .remap_hdp_registers = nbio_v7_2_remap_hdp_registers,
0423 };
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